Kimihiro Ogawa

Path Delay Analysis for Hierarchical Building Block Layout System

Toshio Nakano, Eiji Tamura, Kimihiro Ogawa, 1983, 20th Design Automation Conference Proceedings.

VCO jitter simulation and its comparison with measurement

Kenneth S. Kundert, Masayuki Takahashi, Kimihiro Ogawa, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Estimation of peak current through CMOS VLSI circuit supply lines

Kimihiro Ogawa, Toshio Murayama, Haruhiko Yamaguchi, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

PASTEL: a parameterized memory characterization system

Kimihiro Ogawa, Michinari Kohno, Fusako Kitamura, 1998, Proceedings Design, Automation and Test in Europe.

Path Delay Analysis for Hierarchical Building Block Layout System

Toshio Nakano, Eiji Tamura, Kimihiro Ogawa, 1983, DAC 1983.

Analysis of communication circuits based on multidimensional Fourier transformation

Akio Ushida, Yoshifumi Nishio, Yoshihiro Yamagami, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Stochastic Interpolation Model Scheme and Its Application to Statistical Circuit Analysis (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)

Masayuki Takahashi, Kimihiro Ogawa, Takehiko Adachi, 1994 .

Stochastic interpolation model scheme for statistical circuit design

Andrzej J. Strojwas, Kimihiro Ogawa, Takehiko Adachi, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

A Worst-Case Optimization Approach with Circuit Performance Model Scheme

Masayuki Takahashi, Kimihiro Ogawa, Takehiko Adachi, 1995 .