Har Narayan Upadhyay

发表

Captivating CODEC Stego (CCS): A Cover on Camouflage

K. Thenmozhi, John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, 2013 .

MSB Based Embedding with Integrity: An Adaptive RGB Stego on FPGA Platform

John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, Sundararaman Rajagopala, 2014 .

Undeviating Adaptive Sheltered Cryptography (UASC) method based low power and high secure cache memory design

R. Vijay Sai, Har Narayan Upadhyay, S. Saravanan, 2019, Microprocess. Microsystems.

FPGA Implementation of Self-Testing Logic Gates, Adders and Multipliers

V. Elamaran, Har Narayan Upadhyay, N. Iswarya, 2015 .

LabVIEW Based PIN Hider on ATM Cards: A Transform Domain Secret Concealment Approach

K. Thenmozhi, Rengarajan Amirtharaj, Siva Janakirama, 2014 .

Chaos Blend DNA Coding for Image Encryption on FPGA

Sundararaman Rajagopalan, Siva Janakiraman, Sivaraman Rethinam, 2018, 2018 International Conference on Computer Communication and Informatics (ICCCI).

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

V. Elamaran, Har Narayan Upadhyay, H. Upadhyay, 2017 .

ON-Chip peripherals are ON for chaos - an image fused encryption

Rengarajan Amirtharajan, John Bosco Balaguru Rayappan, Sundararaman Rajagopalan, 2018, Microprocess. Microsystems.

Stego on Song-an Amalgam of vi and FPGA for Hardware Info Hide

John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, Sundararaman Rajagopala, 2014 .

Dual Cellular Automata on FPGA: An Image Encryptors Chip

John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, Sundararaman Rajagopala, 2014 .

Galois Field Proficient Product for Secure Image Encryption on FPGA

Rengarajan Amirtharaj, Sundararaman Rajagopala, Har Narayan Upadhyay, 2014 .

Run-Length Based Efficient Compression for System-on-Chip

S. Saravanan, Har Narayan Upadhyay, A. Balasubram, 2013 .

A Comparative Study of High Speed CMOS Adders using Microwind and FPGA

V. Elamaran, Har Narayan Upadhyay, S. Anusha, 2015 .

Optic assisted image encryption: Confluence of chaos and virtual instrumentation

Rengarajan Amirtharajan, Sundararaman Rajagopalan, Sivaraman Rethinam, 2017, 2017 International Conference on Computer Communication and Informatics (ICCCI).

CMOS VLSI Design of Low Power SRAM Cell Architectures with New TMR: A Layout Approach

V. Elamaran, Har Narayan Upadhyay, H. Upadhyay, 2015 .

Low Power Spatial Modulation Scheme for Wide Band Multiple Input and Multiple Output Wireless Communication Systems

S. Saravanan, Har Narayan Upadhyay, Dhirendra Kumar Tripathi, 2012 .

Low Power Digital Barrel Shifter Datapath Circuits Using Microwind Layout Editor with High Reliability

V. Elamaran, Har Narayan Upadhyay, 2015 .

Logic Elements Consumption Analysis of Cellular Automata Based Image Encryption on FPGA

John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, Sundararaman Rajagopala, 2014 .

Transition Vector Reduction using Segmentation method based on Compression Technique

S. Saravanan, Har Narayan Upadhyay, 2011 .

On the lossless image recovery analysis of cyclic shift and chaotic system based image encryption

Rengarajan Amirtharajan, Sundararaman Rajagopalan, Siva Janakiraman, 2017, 2017 International Conference on Computer Communication and Informatics (ICCCI).

A Case Study of Nanoscale FPGA Programmable Switches with Low Power

V. Elamaran, Har Narayan Upadhyay, H. Upadhyay, 2013 .

Low power look-up table topologies for FPGAs

V. Elamaran, Thadigotla Venkata Subbareddy, Bommepalli Madhava Reddy, 2014, 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT).

Encrypted Biography of Biomedical Image - a Pentalayer Cryptosystem on FPGA

Rengarajan Amirtharajan, John Bosco Balaguru Rayappan, Sundararaman Rajagopalan, 2018, Journal of Signal Processing Systems.

Cellular automata + LFSR + synthetic image: A trio approach to image encryption

Rengarajan Amirtharajan, Sundararaman Rajagopalan, Siva Janakiraman, 2017, 2017 International Conference on Computer Communication and Informatics (ICCCI).

Adapting Scan Based Test Vector for Compression Method Based On Transition Technique

S. Saravanan, Har Narayan Upadhyay, 2012 .

Low Power CMOS Look-Up Tables using PROM

V. Elamaran, Thadigotla Venkata Subbareddy, Har Narayan Upadhyay, 2015 .

Networked hardware assisted key image and chaotic attractors for secure RGB image communication

Rengarajan Amirtharajan, John Bosco Balaguru Rayappan, Sundararaman Rajagopalan, 2017, Multimedia Tools and Applications.

YRBS coding with logistic map – a novel Sanskrit aphorism and chaos for image encryption

Rengarajan Amirtharajan, John Bosco Balaguru Rayappan, Sundararaman Rajagopalan, 2018, Multimedia Tools and Applications.

Gyratory Assisted Info Hide-A Nibble Differencing for Message Embedding

John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, Sundararaman Rajagopala, 2014 .

A Case Study of Impulse Noise Reduction Using Morphological Image Processing with Structuring Elements

V. Elamaran, Har Narayan Upadhyay, K. Narasimhan, 2015 .

REVIEW ON RECENT DEVELOPMENTS IN AUTOMATION OF INDIAN SIGN LANGUAGE

Har Narayan Upadhyay, P. Rajmohan, V. Sivakamasundari, 2016 .

Cellular Automata with Synthetic Image A Secure Image Communication with Transform Domain

Har Narayan Upadhyay, S. Savithri, A. Sridevi, 2019, Defence Science Journal.

Hyper switching memory utilization on hybrid main memory for improved task execution and reduced power consumption

R. Vijay Sai, Har Narayan Upadhyay, M. Prabhu, 2020, Microprocess. Microsystems.

Layer Router for Grayscale Stego - A Hardware Architecture on FPGA and ASIC Platforms

Rengarajan Amirtharajan, John Bosco Balaguru Rayappan, Sundararaman Rajagopalan, 2014 .

Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design

S. Saravanan, Har Narayan Upadhyay, 2012 .

Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern

S. Saravanan, Har Narayan Upadhyay, 2012 .

Minimal Test Coverage of SSFs for the Majority Voters of TMR Configuration

V. Elamaran, G. Rajkumar, Har Narayan Upadhyay, 2018, 2018 International Conference on Control, Power, Communication and Computing Technologies (ICCPCCT).

Hide and seek in silicon - Performance analysis of Quad block Equisum Hardware Steganographic systems

K. Thenmozhi, Sundararaman Rajagopalan, Siva Janakiraman, 2012 .

Fault-tolerant digital filters on FPGA using hardware redundancy techniques

G Rajkumar, Har Narayan Upadhyay, Prasanth Mallavarapu, 2017, 2017 International conference of Electronics, Communication and Aerospace Technology (ICECA).

Modeling Combo PR Generator for Stego Storage Self Test (SSST)

John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, Sundararaman Rajagopala, 2014 .

Space Filling Curve for Data Filling: An Embedded Security Approach

K. Thenmozhi, John Bosco Balaguru Rayappan, Rengarajan Amirtharaj, 2014 .

Improving security against cache memory attacks for dual field multiplier design based on elliptic curve cryptography

Har Narayan Upadhyay, R. Vijay Sai, 2021 .

Design and Implementation of Chao-Cryptic Architecture on FPGA for Secure Audio Communication

Amirtharajan Rengarajan, Sundararaman Rajagopalan, Har Narayan Upadhyay, 2021 .

ENTROPY ANALYSIS FOR ACHIEVING HIGH COMPRESSION RATIO

S. Saravanan, Har Narayan Upadhyay, R. Silambamuthan, 2011 .

A case study of fault-tolerant biological systems with MRI images

Har Narayan Upadhyay, K. Narasimhan, Elamaran, 2017 .