Matthias Müller

Datenskalierung für die verlustleistungsarme Signalverarbeitung in Prozessorsystemen

Matthias Müller, Sven Simon, 2005, GI Jahrestagung.

The impact of clock gating schemes on the power dissipation of synthesizable register files

Andreas Wortmann, Matthias Müller, Sven Simon, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

An instruction set for the efficient implementation of the CORDIC algorithm

Andreas Wortmann, Matthias Müller, Sven Simon, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Register Isolation for Synthesizable Register Files

Andreas Wortmann, Matthias Müller, Sven Simon, 2004, PATMOS.

Low power synthesizable register files for processor and IP cores

Andreas Wortmann, Matthias Müller, Sven Simon, 2006, Integr..

Low power register file architecture for application specific DSPs

Josef A. Nossek, Andreas Wortmann, Matthias Müller, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Light Induced Degradation and Regeneration of High Efficiency Cz PERC Cells with Varying Base Resistivity

Matthias Müller, Gerd Fischer, Torsten Weber, 2013 .

Erhöhung der Wettbewerbsfähigkeit in Industrieunternehmen durch professionelles Multi Utility Management

Matthias Müller, Patrick Weber, Franz Brenner, 2005 .

Battery for portable work tool

Matthias Müller, Harald Mang, Volker Reber, 2010 .

A power efficient register file architecture using master latch sharing

Josef A. Nossek, Andreas Wortmann, Matthias Müller, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Digital signal processor and method for processing data with a digital signal processor

Andreas Wortmann, Matthias Müller, S. Simon, 2002 .

A high-speed transceiver architecture implementable as synthesizable IP core

Andreas Wortmann, Matthias Müller, Sven Simon, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.