Yuh-Min Lin

9 bit 3.3 M samples/S pipelined A-to-D converter using a new mismatch insensitive algorithm

Yalin Ren, Bosco Leung, Yuh-Min Lin, 1999 .

A mismatch-independent DNL pipelined analog-to-digital converter

Yalin Ren, Yuh-Min Lin, B. H. Leung, 1999 .

A 13b 2 . 5-MHz Self-calibrated Pipelined A / D Converter in 3pm CMOS

Beomsup Kim, Yuh-Min Lin, Paul, .