Masato Motomura

发表

FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting

Tetsuya Asai, Kentaro Orimo, Kota Ando, 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects

Masato Motomura, Koichiro Furuta, Toru Awashima, 2012 .

Image steganography based on reaction diffusion models toward hardware implementation

Tetsuya Asai, Alexandre Schmid, Masato Motomura, 2014 .

Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Hideharu Amano, Masato Motomura, Toru Awashima, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic

Masato Motomura, Mahmoud Meribout, 2003, J. Syst. Archit..

A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator

Tetsuya Asai, Masato Motomura, Itaru Hida, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

New Generation Microprocessor Architecture (2):Dynamically Reconfigurable Processor (DRP)

Masato Motomura, Koichiro Furuta, Ryoko Sasaki, 2005 .

Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk

Masato Motomura, Masakazu Yamashina, 2000, ASP-DAC.

Advanced Devices and Architectures

Masato Motomura, Masanori Hariyama, Minoru Watanabe, 2018, Principles and Structures of FPGAs.

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications

Hiroki Nakahara, Masato Motomura, Kengo Nishino, 2018, 2018 IEEE Symposium on VLSI Circuits.

Caching memcached at reconfigurable network interface

Tetsuya Asai, Takashi Takenaka, Hiroaki Inoue, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Programmable logic base cell and array

Masato Motomura, Koichiro Furuta, Taro Fujii, 1999 .

A study of channeled DRAM memory architectures

Masato Motomura, Yoshikazu Yabe, Lars Friebe, 2000, Proceedings 2000 International Conference on Computer Design.

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)

Hiroki Nakahara, Masato Motomura, Hisashi Iwamoto, 2017, FPGA.

20Gbps C-Based Complex Event Processing

Takashi Takenaka, Hiroaki Inoue, Masato Motomura, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Robustness of hardware-oriented restricted Boltzmann machines in deep belief networks for reliable processing

Tetsuya Asai, Alexandre Schmid, Takao Marukame, 2016 .

Foreword

Masato Motomura, Jeffrey C. Gealow, 2016, VLSI Circuits.

A new reconfigurable hardware architecture for high throughput networking applications and its design methodology

Masato Motomura, Mahmoud Meribout, M. Motomura, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Exploring optimized accelerator design for binarized convolutional neural networks

Tetsuya Asai, Kentaro Orimo, Kota Ando, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

d Compilation Challenges for Dynamically Reconfigurable Processors

Hideharu Amano, Masato Motomura, Takao Toi, 2011 .

Achieving higher performance of memcached by caching at network interface

Tetsuya Asai, Takashi Takenaka, Hiroaki Inoue, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation

Tadahiro Kuroda, Tetsuya Asai, Yukitoshi Sanada, 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).

Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

Tetsuya Asai, Masato Motomura, Eric Shun Fukuda, 2014 .

D-23-1 Dynamic Load Generator for Memcached

Tetsuya Asai, Masato Motomura, Eric Shun Fukuda, 2014 .

Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits

Masato Motomura, Jeffrey C. Gealow, 2015, IEEE J. Solid State Circuits.

A memory-based realization of a binarized deep convolutional neural network

Tsutomu Sasao, Hiroki Nakahara, Masato Motomura, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation

Tadahiro Kuroda, Tetsuya Asai, Masato Motomura, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

Hardware Design for C-Based Complex Event Processing

Takashi Takenaka, Hiroaki Inoue, Masato Motomura, 2013 .

Eliminating Hardware Development Difficulties for Software Developers

Tetsuya Asai, Takashi Takenaka, Hideyuki Kawashima, 2013 .

Real-time Tone Mapping: A State of the Art Report

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2020, 2003.03074.

An image sensor/processor 3D stacked module featuring ThruChip interfaces

Tadahiro Kuroda, Tetsuya Asai, Masayuki Ikebe, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

A-combined approach to high-level synthesis for dynamically reconfigurable systems

Masato Motomura, Mahmoud Meribout, M. Meribout, 2004, IEEE Transactions on Computers.

A Hierarchical Cost Estimation Technique for High Level Synthesis

Masato Motomura, Mahmoud Meribout, M. Motomura, 2003, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning

Hiroki Nakahara, Tomoya Fujii, Masato Motomura, 2017, ARC.

6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2017 .

Enhancing Memcached by Caching Its Data and Functionalities at Network Interface

Tetsuya Asai, Takashi Takenaka, Hiroaki Inoue, 2015, J. Inf. Process..

Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks — Their direction of evolutions and optimal roles

Masato Motomura, Takafumi Aoki, Toru Awashima, 2011, 2011 IEEE Cool Chips XIV.

FPGA-Based Design for Motion Vector Estimation Exploiting High-Speed Imaging and Its Application to Motion Classification with Neural Networks

Tadahiro Kuroda, Tetsuya Asai, Masayuki Ikebe, 2014 .

C-Based Complex Event Processing on Reconfigurable Hardware

Takashi Takenaka, Masato Motomura, Hiroaki Inoue, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs

Masato Motomura, Atsuyoshi Nakamura, Shinya Takamaeda-Yamazaki, 2020, ARC.

Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network

Tetsuya Asai, Alexandre Schmid, Takao Marukame, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

A Time-Division Multiplexing Ising Machine on FPGAs

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2017, HEART.

C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join

Tetsuya Asai, Hideyuki Kawashima, Hiroaki Inoue, 2013, ARC.

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC)

Wim Dehaene, Masato Motomura, Yohan Frans, 2019, IEEE J. Solid State Circuits.

A restricted dynamically reconfigurable architecture for low power processors

Tetsuya Asai, Masato Motomura, Itaru Hida, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits

Masato Motomura, Andreia Cathelin, 2016, IEEE J. Solid State Circuits.

Flexible Hardware -What Will Be the Future Development of the Researches on Devices, Architectures, Design Technologies and Applications ?-

Kiyoshi Oguri, Hideharu Amano, Masato Motomura, 1999 .

and Delayed Channel-Replacement Techniques

Masato Motomura, Yoshikazu Yabe, Noritsugu Nakamura, 2000 .

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

Tetsuya Asai, Alexandre Schmid, Takao Marukame, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Excitable Reaction-Diffusion Media with Memristors

Tetsuya Asai, Masato Motomura, Xiyuan Gong, 2012 .

Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI

Kazutoshi Wakabayashi, Masato Motomura, K. Furuta, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems

Marian Verhelst, Meng-Fan Chang, Jun Deguchi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A virtual hardware system on a dynamically reconfigurable logic device

Yuichiro Shibata, Hideharu Amano, Masato Motomura, 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

FPGA Implementation of Single-Image Super Resolution based on Frame-Bufferless Box Filtering

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2013 .

A 300MHzlóbitProgrammable Video Signal Processor ULSIfora Single ChipTeleconferencing Systems

Masahiro Nomura, Masato Motomura, Tadayoshi Enomoto, 1991 .

Low latency divider using ensemble of moving average curves

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Exploiting hardware reconfigurability on window join

Tetsuya Asai, Hideyuki Kawashima, Hiroaki Inoue, 2013, 2013 International Conference on High Performance Computing & Simulation (HPCS).

Implementing and evaluating stream applications on the dynamically reconfigurable processor

Hideharu Amano, Kazutoshi Wakabayashi, Yutaka Yamada, 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines

Tetsuya Asai, Alexandre Schmid, Takao Marukame, 2016 .

FPGA implementation of hardware-oriented reaction-diffusion cellular automata models

Tetsuya Asai, Alexandre Schmid, Masato Motomura, 2015 .

A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM

K. Hirata, Masato Motomura, T. Enomoto, 1990 .

A New Hardware Algorithm for Fast IP Routing Targeting Programmable Routers

Masato Motomura, Mahmoud Meribout, 2003, Net-Con.

Test Compression for Dynamically Reconfigurable Processors

Hiroaki Inoue, Masato Motomura, Koichiro Furuta, 2010, 2010 International Conference on Field Programmable Logic and Applications.

Efficient metrics and high-level synthesis for dynamically reconfigurable logic

Masato Motomura, Mahmoud Meribout, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Stream applications on the dynamically reconfigurable processor

Hideharu Amano, Kazutoshi Wakabayashi, Yutaka Yamada, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

SELECTED PAPER : Noise-Induced Phase Synchronization among Simple Digital Counters (Special Section on Papers Awarded the Student Paper Award at NCSP'12)

Tetsuya Asai, Masato Motomura, Masakazu Matsuura, 2012 .

Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee

Dejan Markovic, Masato Motomura, Byeong-Gyu Nam, 2018, ISSCC.

Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration

Tadahiro Kuroda, Masato Motomura, Yasuhiro Take, 2015, IEICE Trans. Electron..

Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA

Tetsuya Asai, Alexandre Schmid, Takao Marukame, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

An Embedded DRAM-FPGA Chip With Instantaneous Logic Reconfiguration

Masato Motomura, Masakazu Yamashina, Yoshikazu Yabe, 1997, Symposium 1997 on VLSI Circuits.

A Study of Power Consumption in Clocking

Masato Motomura, Masakazu Yamashina, Taro Fujii, 1998 .

Ordered multithreading: a novel technique for exploiting thread-level parallelism

Akihiko Konagaya, Masato Motomura, Sunao Torii, 1995, PACT.

FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2016 .

Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata

Tetsuya Asai, Alexandre Schmid, Masato Motomura, 2016, Int. J. Unconv. Comput..

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS

Masato Motomura, Toshitsugu Sakamoto, Hiromitsu Hada, 2011, 2011 IEEE International Solid-State Circuits Conference.

Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer

Tadahiro Kuroda, Tetsuya Asai, Masayuki Ikebe, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Image Steganography based on Hardware-oriented Reaction-diffusion Models

Tetsuya Asai, Alexandre Schmid, Masato Motomura, 2014 .

Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces

Tadahiro Kuroda, Tetsuya Asai, Masayuki Ikebe, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks pdf

Masato Motomura, Jaehoon Yu, Ángel López García-Arias, 2021, BMVC.

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation

Kota Ando, Masato Motomura, Kazushi Kawamura, 2021, Int. J. Netw. Comput..

Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark

Tetsuya Asai, Masayuki Ikebe, Masato Motomura, 2022, IEEE Transactions on Circuits and Systems for Video Technology.

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner

Hiroki Nakahara, Kota Ando, Masato Motomura, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).

A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning

Masato Motomura, Kazushi Kawamura, Thiem Van Chu, 2021, 2021 International Conference on Field-Programmable Technology (ICFPT).

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training

Masato Motomura, Kazushi Kawamura, Thiem Van Chu, 2021, Int. J. Netw. Comput..

Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines

Kodai Ueyoshi, Masato Motomura, Tetshya Asai, 2015 .

Implementation of a Memory-Efficient Stereo Vision Algorithm Based on 1-D Guided Filtering

Tadahiro Kuroda, Tetsuya Asai, Masayuki Ikebe, 2014 .

Impact of Noise on Spike Transmission through Serially Connected Electrical FitzHugh-Nagumo Circuits with Subthreshold and Suprathreshold Interconductances

Tetsuya Asai, Masato Motomura, Gonzalez-Carabarin Lizeth, 2012 .