Yale N. Patt

Yale N. Patt, Stephen W. Melvin, Michael Shebanow, 1988, [1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21.

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2005, IEEE Transactions on Computers.

Efficient runahead execution processors

Onur Mutlu, Yale N. Patt, O. Mutlu, 2006 .

Researching Novel Systems: To Instantiate, Emulate, Simulate, or Analyticate?

Yale N. Patt, Joel Emer, Doug Burger, 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

Improving branch prediction accuracy by reducing pattern history table interference

Yale N. Patt, Marius Evers, Po-Yung Chang, 1996, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique.

Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers

Yale N. Patt, Pierfrancesco Foglia, Xavier Martorell, 2010 .

EXTENDING A PROLOG MACHINE FOR PARALLEL EXECUTION.

Yale N. Patt, Alvin M. Despain, T. P. Dobry, 1986 .

Greater performance and better efficiency: Predicated execution has shown us the way

Yale N. Patt, 2016, 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT).

High-PerformaGce, High-Reliability Storage Subsystems

Yale N. Patt, Gregory R. Ganger, Robert Y. Hou, 1994 .

COMPARISON OF SEVERAL EVOLVING (UNIVERSITY) SUPERCOMPUTER ARCHITECTURES.

Yale N. Patt, Wen-mei W. Hwu, Robert G. Sheldon, 1984 .

Hardware support for large atomic units in dynamically scheduled machines

Yale N. Patt, S. W. Melvin, Michael C. Shebanow, 1988, MICRO 1988.

Increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Yale N. Patt, Tse-Yu Yeh, Deborah T. Marr, 1993, ICS '93.

Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2006, IEEE Micro.

Multi-core demands multi-interfaces

Yale N. Patt, 2009, HPCA.

Utility-Based Cache Partitioning

Yale N. Patt, Moinuddin K. Qureshi, Y. Patt, 2006 .

Facilitating superscalar processing via a combined static/dynamic register renaming scheme

Yale N. Patt, Eric Sprangle, 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

On tuning the microarchitecture of an HPS implementation of the VAX

Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, 1987, MICRO 20.

Software technology track . Computer architecture task forces

Yale N. Patt, Hesham El-Rewini, Y. Patt, 1997 .

System-oriented evaluation of I/O subsystem performance

Yale N. Patt, Gregory R. Ganger, G. Ganger, 1995 .

Introduction to computing systems - from bits and gates to C and beyond (2. ed.)

Yale N. Patt, Sanjay J. Patel, Y. Patt, 1999 .

Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2005, International Journal of Parallel Programming.

Computer architecture education: mechanical engineers need it too

Yale N. Patt, 1999, WCAE-5 '99.

The V-Way cache: demand-based associativity via global replacement

Yale N. Patt, Moinuddin K. Qureshi, David Thompson, 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

Performance studies of a Prolog machine architecture

Yale N. Patt, Alvin M. Despain, T. P. Dobry, 1985, ISCA '85.

Improving the performance of object-oriented languages with dynamic predication of indirect jumps

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2008, ASPLOS.

Components of a computer architecture education

Yale N. Patt, 1995, WCAE-1 '95.

A Computing Course For All Freshmen Engineering Students (Half Architecture, Half Programming)

Yale N. Patt, Kevin J. Compton, 1997 .

Yoga: A Hybrid Dynamic VLIW/OoO Processor

Yale N. Patt, Rustam Miftakhutdinov, Carlos Villavieja Jos, 2014 .

Metadata update performance in file systems

Yale N. Patt, Gregory R. Ganger, G. Ganger, 1994, OSDI '94.

The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels

Yale N. Patt, Stephen W. Melvin, 1988, SIGMETRICS.

Feedback-directed pipeline parallelism

Yale N. Patt, Moinuddin K. Qureshi, Khubaib, 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

An Area-Efficient Register Alias Table for Implementing HPS

Yale N. Patt, Michael Butler, Y. Patt, 1990, ICPP.

Dynamic Predication of Indirect Jumps

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2007, IEEE Computer Architecture Letters.

The Effect of Instruction Fetch Bandwidth on Value Prediction

Yale N. Patt, Sanjay J. Patel, Marius Evers, 1998, ISCA 1998.

A unifying theory of distributed processing (or, the Chutzpah one should expect when you invite a microarchitect into your sandbox)

Yale N. Patt, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling

Yale N. Patt, Michael Butler, Y. Patt, 1991, MICRO 24.

An experimental single-chip data flow CPU

Yale N. Patt, Wen-mei W. Hwu, Y. Nakagome, 1990 .

HPS IMPLEMENTATION OF VAX; INITIAL DESIGN AND ANALYSIS.

Yale N. Patt, Chien Chen, Wen-mei W. Hwu, 1986 .

Task Forces In Computer Architecture

Yale N. Patt, 1997, Proceedings of the Thirtieth Hawaii International Conference on System Sciences.

Partitioned first-level cache design for clustered microarchitectures

Yale N. Patt, Paul Racunas, 2003, ICS '03.

Alternative implementations of hybrid branch predictors

Yale N. Patt, Eric Hao, Po-Yung Chang, 1995, Proceedings of the 28th Annual International Symposium on Microarchitecture.

Alternative Implementations of Two-Level Adaptive Branch Prediction

Yale N. Patt, Tse-Yu Yeh, Y. Patt, 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.

Design and Implementation of A CMOS Chip for Prolog

Yale N. Patt, Alvin M. Despain, Bruce K. Holmer, 1988 .

DESIGN CHOICES FOR THE HPSm MICROPROCESSOR CHIP.

Yale N. Patt, Wen-mei W. Hwu, Y. Patt, 1987 .

Techniques for Efficient Processing in Runahead Execution Engines

Hyesoon Kim, Onur Mutlu, Yale N. Patt, 2005, ISCA 2005.

Accelerating Critical Section Execution with Asymmetric Multicore Architectures

Onur Mutlu, Yale N. Patt, Moinuddin K. Qureshi, 2010, IEEE Micro.

Toward the specification of an ISA for high performance computing engines. I. The hardware perspective

Yale N. Patt, M. Butler, D. Dyer, 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.

CLARIFICATION OF THE DYNAMIC/STATIC INTERFACE.

Yale N. Patt, Stephen W. Melvin, Y. Patt, 1987 .

Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor

Onur Mutlu, Norman P. Jouppi, Thomas R. Gross, 2016, IEEE Micro.

Wish branches: combining conditional branching and predication for adaptive predicated execution

Onur Mutlu, Yale N. Patt, Jared Stark, 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

Checkpoint repair for out-of-order execution machines

Yale N. Patt, Wen-mei W. Hwu, Y. Patt, 1987, ISCA '87.

Variable length tree structures having minimum average search time

Yale N. Patt, Y. Patt, 1969, CACM.

Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?

Yale N. Patt, Y. Patt, 2006, ISCA 2006.

Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution

Yale N. Patt, Pohua P. Chang, Eric Hao, 1995, International Journal of Parallel Programming.

Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality

Yale N. Patt, Wen-mei W. Hwu, Y. Patt, 1998, 25 Years ISCA: Retrospectives and Reprints.

Aquarius - A High Performance Computing System for Symbolic/Numeric Applications

Yale N. Patt, Alvin M. Despain, Y. Patt, 1985, COMPCON.

Microarchitecture-based introspection: a technique for transient-fault tolerance in microprocessors

Onur Mutlu, Yale N. Patt, Moinuddin K. Qureshi, 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

Microcode and the protection of intellectual effort

Yale N. Patt, John K. Ahlstrom, Y. Patt, 1985, MICRO 18.

Track Piggybacking: An Improved Rebuild Algorithm for RAID5 Disk Arrays

Yale N. Patt, Robert Y. Hou, Y. Patt, 1995, ICPP.

Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2004 .

Adaptive insertion policies for high performance caching

Aamer Jaleel, Yale N. Patt, Moinuddin K. Qureshi, 2007, ISCA '07.

On pipelining dynamic instruction scheduling logic

Yale N. Patt, Jared Stark, Mary D. Brown, 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.

Design decisions influencing the microarchitecture for a Prolog machine

Yale N. Patt, Alvin M. Despain, Tep P. Dobry, 1984, MICRO 17.

Energy Savings via Dead Sub-Block Prediction

Philippe Olivier Alexandre Navaux, Yale N. Patt, Marco Antonio Zanata Alves, 2012, 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing.

Runahead execution: an alternative to very large instruction windows for out-of-order processors

Onur Mutlu, Yale N. Patt, Chris Wilkerson, 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

Single-Threaded vs. Multithreaded: Where Should We Focus?

Derek Chiou, Yale N. Patt, Mark D. Hill, 2007, IEEE Micro.

Efficient Execution of Bursty Applications

Yale N. Patt, Milad Hashemi, Doug Carmean, 2016, IEEE Computer Architecture Letters.

Using System-Level Models to Evaluate I/O Subsystem Designs

Yale N. Patt, Gregory R. Ganger, G. Ganger, 1998, IEEE Trans. Computers.

ImprovingGPUPerformanceviaLargeWarps an dTwo-LevelWarpScheduling

Onur Mutlu, Yale N. Patt, Veynu Narasiman, 2011 .

Real Machines: Design Choices / Engineering Trade-Offs - Guest Editor's Introduction

Yale N. Patt, 1989, Computer.

HPS papers: A retrospective

Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, 2016 .

Tailored Page Sizes

Yale N. Patt, Faruk Guvenilir, Y. Patt, 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

2D-profiling: detecting input-dependent branches with a single input data set

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2006, International Symposium on Code Generation and Optimization (CGO'06).

Predicting Performance Impact of DVFS for Realistic Memory Systems

Yale N. Patt, Rustam Miftakhutdinov, Eiman Ebrahimi, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Implementing a Prolog machine with multiple functional units

Yale N. Patt, Ashok Singhal, 1988, MICRO 1988.

Address-value delta (AVD) prediction: increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

The microprocessor for scientific computing in the year 2000

Yale N. Patt, 1996 .

Guest Editor's Introduction Real Machines: Design Choices/Engineering Trade-Offs

Yale N. Patt, 1989 .

Microarchitectural support for precomputation microthreads

Yale N. Patt, Adi Yoaz, Robert S. Chappell, 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

Prefetch-Aware DRAM Controllers

Onur Mutlu, Yale N. Patt, Veynu Narasiman, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture

Kevin Skadron, Yale N. Patt, Paolo Faraboschi, 2001, MICRO 2001.

The Transformation Hierarchy in the Era of Multi-core

Yale N. Patt, 2007, HiPC.

Prefetch-aware shared-resource management for multi-core systems

Onur Mutlu, Yale N. Patt, Chang Joo Lee, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

Difficult-path branch prediction using subordinate microthreads

Yale N. Patt, Adi Yoaz, Robert S. Chappell, 2002, ISCA.

ImprovingGPUPerformanceviaLargeWarps andTwo-LevelWarpScheduling

Onur Mutlu, Yale N. Patt, Veynu Narasiman, 2011 .

Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching

Aamer Jaleel, Yale N. Patt, Moinuddin K. Qureshi, 2008, IEEE Micro.

SPAM: a microcode based tool for tracing operating system events

Yale N. Patt, Stephen W. Melvin, 1987, MICRO 20.

Optimal and Near-Optimal Universal Logic Modules with Interconnected External Terminals

Yale N. Patt, 1973, IEEE Transactions on Computers.

First courses and fundamentals

Yale N. Patt, Y. Patt, 1996, CSUR.

One Billion Transistors, One Uniprocessor, One Chip

Yale N. Patt, Jared Stark, Sanjay J. Patel, 1997, Computer.

Simultaneous subordinate microthreading (SSMT)

Yale N. Patt, Jared Stark, Steven K. Reinhardt, 1999, ISCA.

Single-threaded vs. multi-threaded

Derek Chiou, Yale N. Patt, Mark D. Hill, 2007 .

HPSm, a high performance restricted data flow architecture having minimal functionality

Yale N. Patt, Wen-mei W. Hwu, Y. Patt, 1986, ISCA '98.

The I/O Subsystem - A Candidate for Improvement: Guest Editor's Introduction

Yale N. Patt, Y. Patt, 1994, Computer.

A High Performance Prolog Processor With Multiple Function Units

Yale N. Patt, Ashok Singhal, Y. Patt, 1989, The 16th Annual International Symposium on Computer Architecture.

Demand-Only Broadcast: Reducing Register File and Bypass Power in Clustered Execution Cores

Yale N. Patt, Mary D. Brown, 2004 .

High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings

Yale N. Patt, Pierfrancesco Foglia, Xavier Martorell, 2010, HiPEAC.

HPS Microarchitecture

Yale N. Patt, Y. Patt, 2011, Encyclopedia of Parallel Computing.

Accelerating critical section execution with asymmetric multi-core architectures

Onur Mutlu, Yale N. Patt, Moinuddin K. Qureshi, 2009, ASPLOS.

An investigation of the performance of various dynamic scheduling techniques

Yale N. Patt, Michael Butler, 1992, MICRO.

The Agree Predictor: A Mechanism For Reducing Negative Branch History Interference

Yale N. Patt, Mitch Alsup, Eric Sprangle, 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.

Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Yale N. Patt, Tse-Yu Yeh, Deborah T. Marr, 2014, ICS 2014.

DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems

Onur Mutlu, Yale N. Patt, Veynu Narasiman, 2010 .

Compiler-Assisted Dynamic Predicated Execution of Complex Control-Flow Structures

Yale N. Patt, Hyesoon Kim Jos, A. Joao, 2006 .

Improving the performance of UCSD Pascal via microprogramming on the PDP-11/60

Yale N. Patt, Mark T. Schaefer, Y. Patt, 1983, SIGM.

Select-free instruction scheduling logic

Yale N. Patt, Mary D. Brown, Jared W. Stark, 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

Performance-aware speculation control using wrong path usefulness prediction

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

Requirements, bottlenecks, and good fortune: agents for microprocessor evolution

Yale N. Patt, 2001 .

Introduction to Computing Systems: From Bits & Gates to C & Beyond

Yale N. Patt, Sanjay J. Patel, 2019 .

Trading disk capacity for performance

Yale N. Patt, Robert Y. Hou, 1993, [1993] Proceedings The 2nd International Symposium on High Performance Distributed Computing.

Branch classification: a new mechanism for improving branch predictor performance

Yale N. Patt, Tse-Yu Yeh, Eric Hao, 1994, MICRO.

Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems

Onur Mutlu, Yale N. Patt, Chang Joo Lee, 2012, TOCS.

The Aquarius Project

Yale N. Patt, Alvin M. Despain, Y. Patt, 1984, COMPCON.

Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors

Yale N. Patt, Tse-Yu Yeh, 1993, Proceedings of the 26th Annual International Symposium on Microarchitecture.

SEVERAL IMPLEMENTATIONS OF PROLOG, THE MICROARCHITECTURE PERSPECTIVE.

Yale N. Patt, Y. Patt, 1986 .

Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order

Yale N. Patt, Jared Stark, Paul Racunas, 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

What Else Is Broken? Can We Fix It?

Yale N. Patt, 2009, SAMOS.

Using non-volatile storage to improve the reliability of RAID5 disk arrays

Yale N. Patt, Robert Y. Hou, 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

Scheduling for Modern Disk Drives and Non-Random Workloads

Richard F. Lary, Joseph Pasquale, Yale N. Patt, 2001 .

Discussion on "AI & Scientific Computing: Are They Incompatible?"

Doug DeGroot, Yale N. Patt, Peter M. Kogge, 1987 .

Hierarchical registers for scientific computers

Yale N. Patt, John A. Swensen, 1988, ICS '88.

The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like?

Yale N. Patt, 2003, HiPC.

Branch Classification: A New Mechanism for Improving Branch Predictor Performance

Yale N. Patt, Tse-Yu Yeh, Eric Hao, 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

HPS, a new microarchitecture: rationale and introduction

Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow, 1985, MICRO 18.

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Onur Mutlu, Yale N. Patt, José A. Joao, 2013, ISCA.

Performance studies of a Prolog machine architecture

Yale N. Patt, Alvin M. Despain, Tep P. Dobry, 1985, ISCA '85.

Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems

Onur Mutlu, Yale N. Patt, Chang Joo Lee, 2010, ASPLOS 2010.

Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?

Yale N. Patt, 2006, CARN.

CMOS CHIP FOR PROLOG.

Vason P. Srini, Yale N. Patt, Alvin M. Despain, 1987 .

Exploiting horizontal and vertical concurrency via the HPSm microprocessor

Yale N. Patt, Wen-mei W. Hwu, Y. Patt, 1987, MICRO 20.

Education in computer science and computer engineering starts with computer architecture

Yale N. Patt, 1996, WCAE-2 '96.

A complex logic module for the synthesis of combinational switching circuits

Yale N. Patt, 1967, AFIPS '67 (Spring).

Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2004, 16th Symposium on Computer Architecture and High Performance Computing.

Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures

Yale N. Patt, Marius Evers, Eric Hao, 2004, International Journal of Parallel Programming.

Microarchitectural support for precomputation microthreads

Yale N. Patt, Adi Yoaz, Robert S. Chappell, 2002, MICRO.

Methodologies for experimental research in computer architecture and performance measurement

Yale N. Patt, 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

A two-level approach to making class predictions

Yale N. Patt, Tse-Yu Yeh, T. Eklund, 2003, 36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the.

Understanding the effects of wrong-path memory references on processor performance

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2004, WMPI '04.

Trace cache design for wide-issue superscalar processors

Yale N. Patt, Sanjay J. Patel, 1999 .

Highest performance computing machines

Yale N. Patt, Y. Patt, 1992, Microprocess. Microprogramming.

Wish Branches: Enabling Adaptive and Aggressive Predicated Execution

Onur Mutlu, Yale N. Patt, Jared Stark, 2006, IEEE Micro.

Run-time generation of HPS microinstructions from a VAX instruction stream

Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, 1986, MICRO 19.

Some results on the asymptotic behavior of functions on subsets of the natural numbers

David F. McAllister, Yale N. Patt, 1979, ACM-SE 17.

Asymmetric Chip Multiprocessors: Balancing Hardware Effic iency and Programmer Efficiency

Yale N. Patt, Eric Sprangle, M. Aater Suleman, 2007 .

Extending a Prolog architecture for high performance numeric computations

Yale N. Patt, Alvin M. Despain, Robert Yung, 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.

Soft updates: a solution to the metadata update problem in file systems

Yale N. Patt, Craig A. N. Soules, Gregory R. Ganger, 2000 .

Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

A comparison of dynamic branch predictors that use two levels of branch history

Yale N. Patt, Tse-Yu Yeh, Y. Patt, 1993, ISCA '93.

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Yale N. Patt, Moinuddin K. Qureshi, Y. Patt, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Prefetch-Aware Memory Controllers

Onur Mutlu, Yale N. Patt, Veynu Narasiman, 2011, IEEE Transactions on Computers.

VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2007, ISCA '07.

Handling of packet dependencies: a critical issue for highly parallel network processors

Yale N. Patt, Stephen W. Melvin, 2002, CASES '02.

Optimal andNear-Optimal Universal Logic Modules withInterconnected External Terminals

Yale N. Patt, Y. Patt, 1973 .

Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers

Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, 1986, COMPCON.

Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic—Implementation Issues, Measurements, and Analysis

Yale N. Patt, David B. Aspinwall, Y. Patt, 1985, IEEE Transactions on Computers.

Some Clarifications of the Concept of a Garden-of-Eden Configuration

Serafino Amoroso, Yale N. Patt, Gerald Cooper, 1975, J. Comput. Syst. Sci..

Minimum Search Tree Structures for Data Partitioned into Pages

Yale N. Patt, 1972, IEEE Transactions on Computers.

Alternative implementations of hybrid branch predictors

Yale N. Patt, Eric Hao, Po-Ying Chang, 1995, MICRO 1995.

A microcode-based environment for noninvasive performance analysis

Yale N. Patt, Stephen W. Melvin, 1986, MICRO 19.

Issues and problems in the I/O subsystem. I. The magnetic disk

Yale N. Patt, Gregory R. Ganger, Robert Y. Hou, 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

Yale N. Patt, Chris Wilkerson, Milad Hashemi, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Checkpoint Repair for High-Performance Out-of-Order Execution Machines

Yale N. Patt, Wen-mei W. Hwu, Y. Patt, 1987, IEEE Transactions on Computers.

Alternative implementations of two-level adaptive branch prediction

Yale N. Patt, Tse-Yu Yeh, Y. Patt, 1992, ISCA '92.

Line Distillation: A Mechanism to Improve Cache Utilization

Yale N. Patt, Moinuddin K. Qureshi, David A. Thompson, 2006 .

The Challenges of Multicore: Information and Mis-Information

Yale N. Patt, 2009, ARCS.

Single instruction stream parallelism is greater than two

Yale N. Patt, Michael Shebanow, Michael Butler, 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.

A Comparison Of Dynamic Branch Predictors That Use Two Levels Of Branch History

Yale N. Patt, Tse-Yu Yeh, Y. Patt, 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.

Fast temporary storage for serial and parallel execution

Yale N. Patt, John A. Swensen, 1987, ISCA '87.

High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation

Yale N. Patt, Alvin M. Despain, Wayne Citrin, 1986, COMPCON.

Top Picks [Guest editors' introduction]

Onur Mutlu, Yale N. Patt, 2011, IEEE Micro.

High performance supercomputers: should the individual processor be more than a brick?

Yale N. Patt, 2012, ICS '12.

Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches

Yale N. Patt, Marius Evers, Po-Yung Chang, 1996, ISCA.

Improving memory Bank-Level Parallelism in the presence of prefetching

Onur Mutlu, Yale N. Patt, Veynu Narasiman, 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Continuous runahead: Transparent hardware acceleration for memory intensive workloads

Onur Mutlu, Yale N. Patt, Milad Hashemi, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Select-free instruction scheduling logic

Yale N. Patt, Jared Stark, Mary D. Brown, 2001, MICRO.

Can They Be Fixed: Some Thoughts After 40 Years in the Business

Yale N. Patt, 2008, SAMOS.

Techniques for efficient processing in runahead execution engines

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

Critical issues regarding HPS, a high performance microarchitecture

Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, 1985, MICRO 18.

Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2007, International Symposium on Code Generation and Optimization (CGO'07).

Comparing rebuild algorithms for mirrored and RAID5 disk arrays

Yale N. Patt, Robert Y. Hou, 1993, SIGMOD '93.

Retrospective: alternative implementations of two-level adaptive training branch prediction

Yale N. Patt, Tse-Yu Yeh, Y. Patt, 1998, ISCA '98.

Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems

Onur Mutlu, Yale N. Patt, Chang Joo Lee, 2012, ACM Trans. Comput. Syst..

Comparison of Aquarius and SPUR (Symbolic Processing upon RISC) Projects

Yale N. Patt, Alvin M. Despain, Randy H. Katz, 1985 .

The process-flow model: examining I/O performance from the system's point of view

Yale N. Patt, Gregory R. Ganger, G. Ganger, 1993, SIGMETRICS '93.

Data marshaling for multi-core architectures

Onur Mutlu, Yale N. Patt, José A. Joao, 2010, ISCA.

Accelerating Dependent Cache Misses with an Enhanced Memory Controller

Onur Mutlu, Yale N. Patt, Milad Hashemi, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

Runahead Execution: An Effective Alternative to Large Instruction Windows

Onur Mutlu, Yale N. Patt, Chris Wilkerson, 2003, IEEE Micro.

Dynamic Predication of Indirect Jumps

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2007, IEEE Computer Architecture Letters.

An effective programmable prefetch engine for on-chip caches

Yale N. Patt, Eric Hao, Po-Ying Chang, 1995, MICRO 1995.

Experimental Research in Computer Architecture - Guest Editor's Introduction to the Special Issue

Yale N. Patt, Y. Patt, 1991, Computer.

The I/O Subsvstem

Yale N. Patt, 1994 .

Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses

Onur Mutlu, Yale N. Patt, Hyesoon Kim, 2006, IEEE Transactions on Computers.

Improving branch prediction accuracy by reducing pattern history table interference

Yale N. Patt, Marius Evers, Po-Yung Chang, 2007, International Journal of Parallel Programming.

On pipelining dynamic instruction scheduling logic

Yale N. Patt, Jared Stark, Mary D. Brown, 2000, MICRO 33.

The effect of speculatively updating branch history on branch prediction accuracy, revisited

Yale N. Patt, Eric Hao, Po-Yung Chang, 1994, MICRO 27.

Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing

Harry F. Jordan, Benjamin W. Wah, Tse-Yun Feng, 1992, J. Parallel Distributed Comput..

Bottleneck identification and scheduling in multithreaded applications

Onur Mutlu, Yale N. Patt, José A. Joao, 2012, ASPLOS XVII.

The V-Way Cache: Demand Based Associativity via Global Replacement

Yale N. Patt, Moinuddin K. Qureshi, David A. Thompson, 2005, ISCA 2005.

Microarchitecture choices (implementation of the VAX)

Yale N. Patt, 1989, MICRO 22.

Feedback Driven Pipelining

Yale N. Patt, M. Aater, Suleman Moinuddin, 2010 .

Keynote 1 - VLSI 2.0: R&D Post Moore

Sani R. Nassif, Magdy S. Abadir, Yale N. Patt, 2013, VLSI-SoC.

PUP: An Architecture to Exploit Parallel Unification in Prolog

Yale N. Patt, Chien Chen, Ashok Singhal, 1988 .

Unification Parallelism: How Much Can We Exploit?

Yale N. Patt, Ashok Singhal, Y. Patt, 1989, NACLP.

Opening and keynote 1

Yale N. Patt, 2004, ISPASS.

Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Yale N. Patt, Tse-Yu Yeh, Deborah T. Marr, 2014, ICS 25th Anniversary.

An analysis of correlation and predictability: what makes two-level branch predictors work

Yale N. Patt, Sanjay J. Patel, Marius Evers, 1998, ISCA.

Alternative fetch and issue policies for the trace cache fetch mechanism

Yale N. Patt, Sanjay J. Patel, Daniel H. Friendly, 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems

Onur Mutlu, Yale N. Patt, Eiman Ebrahimi, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

A comprehensive instruction fetch mechanism for a processor supporting speculative execution

Yale N. Patt, Tse-Yu Yeh, 1992, MICRO 25.

A comprehensive instruction fetch mechanism for a processor supporting speculative execution

Yale N. Patt, Tse-Yu Yeh, Y. Patt, 1992, MICRO 1992.

Foreword

Kevin Skadron, Jean-Luc Gaudiot, Yale N. Patt, 2006, IEEE Comput. Archit. Lett..

Implementing a Prolog Machine with Multiple Functional Units

Yale N. Patt, Ashok Singhal, Y. Patt, 1988, [1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21.

Increasing the instruction fetch rate via multiple branch prediction and a branch address cache

Yale N. Patt, Deborah T. Marr, Tse-Yu Yeh, 1993, ICS '93.

BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches

Yale N. Patt, Sangkug Lym, Stephen Pruett, 2020, 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Alternative proposals for implementing Prolog concurrently and implications regarding their respective microarchitectures

Carl Ponder, Yale N. Patt, 1984, MICRO 17.

Teaching and teaching computer architecture: two very different topics: (some opinions about each)

Yale N. Patt, 2003, WCAE '03.

On-line extraction of SCSI disk drive parameters

Yale N. Patt, Gregory R. Ganger, Bruce L. Worthington, 1995, SIGMETRICS '95/PERFORMANCE '95.

Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication

Philip G. Emma, Yale N. Patt, Rustam Miftakhutdinov, 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A Case for MLP-Aware Cache Replacement

Onur Mutlu, Yale N. Patt, Moinuddin K. Qureshi, 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

Using internal redundant representations and limited bypass to support pipelined adders and register files

Yale N. Patt, Mary D. Brown, 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

Alternative implementations of Prolog: the microarchitecture perspective

Yale N. Patt, 1989, IEEE Trans. Syst. Man Cybern..

The effects of mispredicted-path execution on branch prediction structures

Yale N. Patt, Stéphan Jourdan, Jared Stark, 1996, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique.

The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints?

Yale N. Patt, 2005, AICCSA.

Improving branch prediction by understanding branch behavior

Yale N. Patt, Marius Evers, 2000 .

Parallel application memory scheduling

Chris Fallin, Onur Mutlu, Yale N. Patt, 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

AchievingOut-of-OrderPerformancewithAlmostIn-OrderComplexity

Yale N. Patt, Francis Tseng, 2008 .

C COMPILER FOR HPS I, A HIGHLY PARALLEL EXECUTION ENGINE.

Yale N. Patt, Wen-mei W. Hwu, Michael C. Shebanow, 1986 .

DRAM-Aware Last-Level Cache Replacement

Onur Mutlu, Yale N. Patt, Chang Joo, 2010 .

The use of microcode instrumentation for development, debugging and tuning of operating system kernels

Yale N. Patt, S. W. Melvin, 1988, SIGMETRICS 1988.

Disk subsystem load balancing: disk striping vs. conventional data placement

Yale N. Patt, Gregory R. Ganger, Robert Y. Hou, 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors

Yale N. Patt, Tse-Yu Yeh, 1993, MICRO 1993.

Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs

Yale N. Patt, Moinuddin K. Qureshi, M. Aater Suleman, 2008, ASPLOS.

Target prediction for indirect jumps

Yale N. Patt, Eric Hao, Po-Yung Chang, 1997, ISCA '97.

Tailoring functional units and memory in a high performance Prolog architecture

Yale N. Patt, Ashok Singhal, Y. Patt, 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.

Flexible reference-counting-based hardware acceleration for garbage collection

Onur Mutlu, Yale N. Patt, José A. Joao, 2009, ISCA '09.

Modifications to the VAX-11/780 microarchitecture to support IEEE floating point arithmetic

Yale N. Patt, David B. Aspinwall, 1983, SIGM.

Multi-core demands multi-interfaces

Yale N. Patt, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

Filtered runahead execution with a runahead buffer

Yale N. Patt, Milad Hashemi, Y. Patt, 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Data Marshaling for Multicore Systems

Onur Mutlu, Yale N. Patt, José A. Joao, 2011, IEEE Micro.

Scheduling algorithms for modern disk drives

Yale N. Patt, Gregory R. Ganger, Bruce L. Worthington, 1994, SIGMETRICS 1994.