Arani Sinha

发表

Analog/Mixed Signal IP DFx from a Foundry perspective

Yonghyun Kim, Salem Abdennadher, Arani Sinha, 2019, 2019 IEEE Latin American Test Symposium (LATS).

Simulating the Effects of Process Variations on Capacitive Crosstalk

Shahin Nazarian, T. M. Mak, Arani Sinha, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design

Irith Pomeranz, Srikanth Venkataraman, Naixing Wang, 2019, ACM Trans. Design Autom. Electr. Syst..

Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests

Arani Sinha, Ankit Shah, Raman Nayyar, 2020, IEEE Design & Test.

Test generation for capacitance and inductance induced noise on interconnects in vlsi logic

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2006 .

Innovative practices session 1C screening for layout sensitive defects

Arani Sinha, Nitin Chaudhary, 2017, VTS.

Validation and test generation for oscillatory noise in VLSI interconnects

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?

Arani Sinha, 2010, VTS.

The buck stops with wafer test: Dream or reality?

Suriyaprakash Natarajan, Arani Sinha, 2011, 29th VLSI Test Symposium.

A Novel mechanism for speed characterization during delay test

Yan Dong, Nehal Patel, Amitava Majumdar, 2011, 29th VLSI Test Symposium.

Path selection based on static timing analysis considering input necessary assignments

Irith Pomeranz, Bo Yao, Arani Sinha, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines

Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Location of the Largest Empty Rectangle among Arbitrary Obstacles

Subhas C. Nandy, Bhargab B. Bhattacharya, Arani Sinha, 1994, FSTTCS.

The bang for the buck with resiliency: Yield or field?

Suriyaprakash Natarajan, Arani Sinha, 2011, 29th VLSI Test Symposium.

An enhanced test generator for capacitance induced crosstalk delay faults

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2003, 2003 Test Symposium.

DFM-aware fault model and ATPG for intra-cell and inter-cell defects

Ayush Singhal, Alodeep Sanyal, Arani Sinha, 2017, 2017 IEEE International Test Conference (ITC).

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2008, 2008 17th Asian Test Symposium.

Panel: Analog Characterization and Test: The Long Road to Realization

Amitava Majumdar, Arani Sinha, Vasu Ganti, 2009, 2009 27th IEEE VLSI Test Symposium.

Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction

Sandip Ray, Arani Sinha, 2021, 2021 IEEE European Test Symposium (ETS).

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts

Abhijit Chatterjee, Suriyaprakash Natarajan, Arani Sinha, 2021, 2021 IEEE 39th VLSI Test Symposium (VTS).