Melvin A. Breuer

Melvin A. Breuer, Sandeep K. Gupta, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Testing for Bridging Faults

Melvin A. Breuer, Arthur D. Friedman, Miron Abramovici, 1990 .

Optimal Seguencing of Scan Registers

Melvin A. Breuer, Sridhar Narayanan, Charles Njinda, 1992, Proceedings International Test Conference 1992.

Test generation for crosstalk-induced faults: framework and computational results

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

A Unified Approach for the Synthesis of Scalable and Testable Embedded Architectures

Melvin A. Breuer, Viktor K. Prasanna, Chouki Aktouf, 1998 .

An O(n) algorithm for width determination of power/ground routes for VLSI circuits

Melvin A. Breuer, Salim U. Chowdhury, 1986, Integr..

Optimal routing of two rectangular blocks

Melvin A. Breuer, Mandalagiri S. Chandrasekhar, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A test and maintenance controller for a module containing testable chips

Melvin A. Breuer, Jung-Cheun Lien, J. Lien, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

Fast optimal diagnosis procedures for k-out-of-n:G systems

Melvin A. Breuer, S. Salloum, 1997 .

Testing for Single Stuck Faults

Melvin A. Breuer, Arthur D. Friedman, Miron Abramovici, 1990 .

Clarifying the record on testability cost functions

Melvin A. Breuer, 2008, IEEE Design & Test of Computers.

Configuring multiple scan chains for minimum test time

Melvin A. Breuer, Sridhar Narayanan, Rajesh Gupta, 1992, ICCAD.

Test generation for capacitance and inductance induced noise on interconnects in vlsi logic

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2006 .

A Placement Algorithm for Array Processors

Melvin A. Breuer, Dah-Juh Chyan, 1983, 20th Design Automation Conference Proceedings.

GlYFF: A Framework for Global Yield and

Melvin A. Breuer, Shuo Wang, Yue Gao, 2015 .

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2009, 2009 Asian Test Symposium.

Multi-media applications and imprecise computation

Melvin A. Breuer, M. Breuer, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

A novel test methodology based on error-rate to support error-tolerance

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2005, IEEE International Conference on Test, 2005..

Estimating Error Rate in Defective Logic Using Signature Analysis

Melvin A. Breuer, Zhaoliang Pan, M. Breuer, 2007, IEEE Transactions on Computers.

Probabilistic Aspects of Boolean Switching Functions via a New Transform

Melvin A. Breuer, Sarangan Krishna Kumar, M. Breuer, 1981, JACM.

Multiple tests for each gate delay fault: higher coverage and lower test application cost

Melvin A. Breuer, Sandeep K. Gupta, Shahdad Irajpour, 2005, IEEE International Conference on Test, 2005..

A new framework for static timing analysis, incremental timing refinement, and timing simulation

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

Ordering storage elements in a single scan chain

Melvin A. Breuer, Rajesh Gupta, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Detectability of CMOS stuck-open faults using random and pseudorandom test sequences

Melvin A. Breuer, Sarma Sastry, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimum Placement of Two Rectangular Blocks

Melvin A. Breuer, Mandalagiri S. Chandrasekhar, 1982, DAC 1982.

Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models

Melvin A. Breuer, S. Irajpour, S. K. Gupta, 2004 .

Testable MUTEX Design

Melvin A. Breuer, Peter A. Beerel, Matheus T. Moreira, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Bounds on pseudoexhaustive test lengths

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Novel test pattern generators for pseudo-exhaustive testing

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 1993, Proceedings of IEEE International Test Conference - (ITC).

A Note on Three-Valued Logic Simulation

Melvin A. Breuer, 1972, IEEE Transactions on Computers.

Validation and test generation for oscillatory noise in VLSI interconnects

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

The design of self-checking multi-output combinational circuits

Melvin A. Breuer, Danny C. C. Ko, 1977, AFIPS '77.

Switch-level delay test of domino logic circuits

Melvin A. Breuer, Sandeep K. Gupta, Suriyaprakash Natarajan, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

TA-PSV—Timing Analysis for Partially Specified Vectors

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2002, J. Electron. Test..

Optimum design of IC power/ground nets subject to reliability constraints

Melvin A. Breuer, Salim U. Chowdhury, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Reconfiguration techniques for a single scan chain

Melvin A. Breuer, Sridhar Narayanan, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Concurrent control of multiple BIT structures

Melvin A. Breuer, Sandeep K. Gupta, Jung-Cheun Lien, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

The application of integer programming in design automation

Melvin A. Breuer, 1966, DAC.

Estimation of BIST Resources During High-Level Synthesis

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, J. Electron. Test..

An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Optimal Configuring of Multiple Scan Chains

Melvin A. Breuer, Sridhar Narayanan, Rajesh Gupta, 1993, IEEE Trans. Computers.

Recent developments in the automated design and analysis of digital systems

Melvin A. Breuer, 1972 .

A methodology for custom VLSI layout

Melvin A. Breuer, Anshul Kumar, 1983, IEEE Transactions on Systems, Man, and Cybernetics.

A Survey of the State of the Art of Design Automation

Melvin A. Breuer, Arthur D. Friedman, Alexander Iosupovicz, 1981, Computer.

Test generation for crosstalk-induced delay in integrated circuits

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Determining error rate in error tolerant VLSI chips

Melvin A. Breuer, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

SWiTEST: a switch level test generation system for CMOS combinational circuits

Melvin A. Breuer, Kuen-Jong Lee, Charles A. Njinda, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Modeling and simulation for crosstalk aggravated by weak-bridge defects between on-chip interconnects

Melvin A. Breuer, Sandeep K. Gupta, Lei Wang, 2004, 13th Asian Test Symposium.

Reliable Design—Theory and Techniques

Melvin A. Breuer, Arthur D. Friedman, 1976 .

An Error Rate Based Test Methodology to Support Error-Tolerance

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2008, IEEE Transactions on Reliability.

Adaptive Computers

Melvin A. Breuer, 1967, Inf. Control..

GlYFF: A framework for global yield and floorplan aware design optimization

Yue Gao, Melvin A. Breuer, Shuo Wang, 2015, Sixteenth International Symposium on Quality Electronic Design.

Identification of Multiple Stuck-Type Faults in Combinational Networks

Melvin A. Breuer, Stephen Y. H. Su, Shih-Jeh Chang, 1976, IEEE Transactions on Computers.

Recent Developments in Design Automation

Melvin A. Breuer, M. Breuer, 1972, Computer.

Analytical models for crosstalk excitation and propagation in VLSI circuits

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Performance Optimization and Analysis of Blade Designs under Delay Variability

Melvin A. Breuer, Peter A. Beerel, Matheus T. Moreira, 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.

Data Path Allocation Techniques for High-level Synthesis of Low BIST Area Overhead Designs

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 2007 .

A new method for assigning signal flow directions to MOS transistors

Melvin A. Breuer, Rajiv Gupta, Kuen-Jong Lee, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Optimum Placement of Two Rectangular Blocks

Melvin A. Breuer, Mandalagiri S. Chandrasekhar, 1982, 19th Design Automation Conference.

Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Analysis of ground bounce in deep sub-micron circuits

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 1993, 30th ACM/IEEE Design Automation Conference.

Process variations and their impact on circuit operation

Melvin A. Breuer, Sandeep K. Gupta, Suriyaprakash Natarajan, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

Reconfigurable scan chains: A novel approach to reduce test application time

Melvin A. Breuer, Sridhar Narayanan, S. Narayanan, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

An error-oriented test methodology to improve yield with error-tolerance

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2006, 24th IEEE VLSI Test Symposium.

Fault Diagnosis Based on Effect-Cause Analysis: An Introduction

Melvin A. Breuer, Miron Abramovici, 1980, 17th Design Automation Conference.

Some theoretical aspects of algorithmic routing

Melvin A. Breuer, Prathima Agrawal, 1977, DAC '77.

Efficient identification of crosstalk induced slowdown targets

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2004, 13th Asian Test Symposium.

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Automatic Design for Testability Via Testability Measures

Melvin A. Breuer, Ting-Hua Chen, 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Digital System Simulation: Current Status and Future Trends or Darwin's Theory of Simulation

Melvin A. Breuer, Alice C. Parker, 1981, 18th Design Automation Conference.

Partial scan design of register-transfer level circuits

Melvin A. Breuer, Rajesh Gupta, Rajesh K. Gupta, 1995, J. Electron. Test..

Let's think analog

Melvin A. Breuer, M. Breuer, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Testability properties of acyclic structures and applications to partial scan design

Melvin A. Breuer, Rajesh Gupta, Rajesh K. Gupta, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Design for Testability

Melvin A. Breuer, Arthur D. Friedman, Miron Abramovici, 1990 .

Test Schedules for VLSI Circuits Having Built-In Test Hardware

Melvin A. Breuer, Magdy S. Abadir, M. Breuer, 1986, IEEE Transactions on Computers.

A new gate delay model for simultaneous switching and its applications

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2001, DAC '01.

Test Generation for Sequential Circuits

Melvin A. Breuer, Arthur D. Friedman, A. D. Friedman, 1976 .

FunctionalPartitioning and Simulation of DigitalCircuits

Melvin A. Breuer, 1970 .

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 2002, J. Electron. Test..

Implementation of Threshold Nets by Integer Linear Programming

Melvin A. Breuer, 1965, IEEE Trans. Electron. Comput..

Allocation Techniques for Reducing BIST Area Overhead of Data Paths

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, J. Electron. Test..

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis

Melvin A. Breuer, Miron Abramovici, M. Breuer, 1980, IEEE Transactions on Computers.

Test generation for ground bounce in internal logic circuitry

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

A universal test sequence for CMOS scan registers

Melvin A. Breuer, Kuen-Jong Lee, M. Breuer, 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

Test generation for maximizing ground bounce for internal circuitry with reconvergent fan-outs

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Position Statement: Noise: Whose Problem Is It Anyway

Melvin A. Breuer, 2000 .

Design and Analysis of Testable Mutual Exclusion Elements

Melvin A. Breuer, Peter A. Beerel, Matheus T. Moreira, 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.

High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability

Melvin A. Breuer, 2000, VTS.

An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping

Melvin A. Breuer, Rajesh Gupta, Rajiv Gupta, 1989, Computer.

On Routing for Custom Integrated Circuits

Melvin A. Breuer, Abbas El Gamal, Zahir A. Syed, 1982, 19th Design Automation Conference.

State-of-the-Art Assessment of Testing and Testability of Custom LSI/VLSI Circuits. Volume III. Fault Model Analysis.

Melvin A. Breuer, A. J. Carlan, 1982 .

MAXIMAL DIAGNOSIS FOR WIRING NETWORKS

Melvin A. Breuer, Jung-Cheun Lien, J. Lien, 1991, 1991, Proceedings. International Test Conference.

Analyzing crosstalk in the presence of weak bridge defects

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

STAX: Statistical Crosstalk Target Set Compaction

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Challenges for the academic test community

Melvin A. Breuer, 2000, Proceedings of the Ninth Asian Test Symposium.

A Survey of the State-of-the-Art of Design Automation - An Invited Presentation

Melvin A. Breuer, 1982, DAC 1982.

Scan Path with Look Ahead Shifting (SPLASH)

Melvin A. Breuer, Magdy S. Abadir, 1986, ITC.

An IEEE 1149.1 Compliant Test Control Architecture

Melvin A. Breuer, Debaditya Mukherjee, M. Breuer, 1998, J. Electron. Test..

Roving Emulation as a Fault Detection Mechanism

Melvin A. Breuer, Asad A. Ismaeel, A. A. Ismaeel, 1986, IEEE Transactions on Computers.

A Module Interchange Placement Machine

Melvin A. Breuer, Alexander Iosupovicz, Clarence King, 1983, 20th Design Automation Conference Proceedings.

Fault tolerance in linear systolic arrays using time redundancy

Melvin A. Breuer, Cauligi S. Raghavendra, A. Majumdar, 1988 .

A Knowledge Based System for Selecting a Test Methodology for a PLA

Melvin A. Breuer, Xi-an Zhu, 1985, DAC 1985.

Test embedding with discrete logarithms

Melvin A. Breuer, Sandeep K. Gupta, Mody Lempel, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Extraction of a Highlevel Structural Representation from Circuit Descriptions with Applications to DFT/BIST "Lambda

Melvin A. Breuer, Charles Njinda, Ishwar Parulkar, 1994, 31st Design Automation Conference.

On Redundancy and Fault Detection in Sequential Circuits

Melvin A. Breuer, Miron Abramovici, 1979, IEEE Transactions on Computers.

Scheduling and module assignment for reducing BIST resources

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, Proceedings Design, Automation and Test in Europe.

Vector representation of switching and three-valued functions

Melvin A. Breuer, Ytzhak Levendel, 1978, MVL '78.

Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect–Cause Analysis

Melvin A. Breuer, Miron Abramovici, M. Breuer, 1982, IEEE Transactions on Computers.

Optimal Sequencing of Scan l%egiste!rs*

Melvin A. Breuer, Sridhar Narayanan, Charles A. Njinda, 1992 .

Defect and error tolerance in the presence of massive numbers of defects

Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak, 2004, IEEE Design & Test of Computers.

An integrated system for assigning signal flow directions to CMOS transistors

Melvin A. Breuer, Rajiv Gupta, Kuen-Jong Lee, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Asynchronous multiple scan chains

Melvin A. Breuer, Sridhar Narayanan, S. Narayanan, 1995, Proceedings 13th IEEE VLSI Test Symposium.

An extensible user interface for an object-oriented VLSI CAD framework

Melvin A. Breuer, Rajiv Gupta, 1990, Systems Integration '90. Proceedings of the First International Conference on Systems Integration.

Techniques for the simulation of computer logic

Melvin A. Breuer, 1964, CACM.

Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER)

Melvin A. Breuer, Zhaoliang Pan, M. Breuer, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Hardware fault detection

Melvin A. Breuer, 1968, AFIPS '68 (Fall, part II).

An optimal scheduling algorithm for testing interconnect using boundary scan

Melvin A. Breuer, Jung-Cheun Lien, 1991, J. Electron. Test..

A Knowledge-Based TDM Selection System

Melvin A. Breuer, Xi-an Zhu, M. Breuer, 1986, FJCC.

Test generation for maximizing ground bounce considering circuit delay

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Roving Emulation asa FaultDetection Mechanism

Melvin A. Breuer, Asad A. Ismaeel, A. A. Ismaeel, 1986 .

Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware

Melvin A. Breuer, Charles Njinda, Debaditya Mukherjee, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Design automation of digital systems

Melvin A. Breuer, M. Breuer, 1972 .

Hardware that produces bounded rather than exact results

Melvin A. Breuer, M. Breuer, 2010, Design Automation Conference.

The probability of error detection in sequential circuits using random test vectors

Melvin A. Breuer, Asad A. Ismaeel, 1991, J. Electron. Test..

On detecting single and multiple bridging faults in CMOS circuits using the current supply monitoring method

Melvin A. Breuer, Kuen-Jong Lee, M. Breuer, 1990, IEEE International Symposium on Circuits and Systems.

Identification ofMultiple Stuck-Type Faults inCombinational Networks

Melvin A. Breuer, Stephen Y. H. Su, 1976 .

Initial design concepts for an advanced design automation system

Melvin A. Breuer, Arthur D. Friedman, 1974, DAC '74.

A probabilistic model for the analysis of the routing process for circuits

Melvin A. Breuer, Prathima Agrawal, 1980, Networks.

Analytic models for crosstalk delay and pulse analysis under non-ideal inputs

Melvin A. Breuer, Sandeep K. Gupta, Weiyu Chen, 1997, Proceedings International Test Conference 1997.

A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing

Melvin A. Breuer, Charles Njinda, Rajagopalan Srinivasan, 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays

Melvin A. Breuer, Israel Koren, M. Breuer, 1984, IEEE Transactions on Computers.

Introducing redundant computations in RTL data paths for reducing BIST resources

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 2001, TODE.

Fault tolerance in linear systolic arrays using time redundancy

Melvin A. Breuer, Cauligi S. Raghavendra, A. Majumdar, 1990, [1988] Proceedings of the Twenty-First Annual Hawaii International Conference on System Sciences. Volume I: Architecture Track.

Simplification of the Covering Problem with Application to Boolean Expressions

Melvin A. Breuer, M. Breuer, 1970, JACM.

Functional Partitioning and Simulation of Digital Circuits

Melvin A. Breuer, M. Breuer, 1970, IEEE Transactions on Computers.

The BALLAST Methodology for Structured Partial Scan Design

Melvin A. Breuer, Rajesh Gupta, Rajiv Gupta, 1990, IEEE Trans. Computers.

A methodology for custom VLSI layout

Melvin A. Breuer, A. Kumar, 1983 .

Error-tolerance and multi-media

Melvin A. Breuer, Haiyang Zhu, M. Breuer, 2006, 2006 International Conference on Intelligent Information Hiding and Multimedia.

HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2010, 2010 19th IEEE Asian Test Symposium.

Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models

Melvin A. Breuer, Sandeep K. Gupta, Shahdad Irajpour, 2004, 2004 International Conferce on Test.

Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults

Melvin A. Breuer, Kuen-Jong Lee, M. Breuer, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault Detection in a Linear Cascade of Identical Machines

Melvin A. Breuer, 1968, SWAT.

Fundamental CAD algorithms

Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An enhanced test generator for capacitance induced crosstalk delay faults

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2003, 2003 Test Symposium.

The Effects of Races, Delays, and Delay Faults on Test Generation

Melvin A. Breuer, 1974, IEEE Transactions on Computers.

Novel Test Pattern Generators for Pseudoexhaustive Testing

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 2000, IEEE Trans. Computers.

Merging multiple FSM controllers for DFT/BIST hardware

Melvin A. Breuer, Massoud Pedram, Debaditya Mukherjee, 1993, ICCAD.

Lower bounds on test resources for scheduled data flow graphs

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1996, DAC '96.

Digital Systems Testing & Testable Design

Melvin A. Breuer, Miron Abramovici, Allan D. Friedman, 1993 .

Concurrent fault simulation and functional level modeling

Melvin A. Breuer, Miron Abramovici, K. Kumar, 1977, DAC '77.

Testing for Intermittent Faults in Digital Circuits

Melvin A. Breuer, M. Breuer, 1973, IEEE Transactions on Computers.

A new paradigm for trading off yield, area and performance to enhance performance per wafer

Yue Gao, Melvin A. Breuer, Yanzhi Wang, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits

Melvin A. Breuer, 1971, IEEE Transactions on Computers.

Knowledge based systems for test and diagnosis : proceedings of the IFIP WG 10.5 International Workshop on Knowledge Based Systems for Test and Diagnosis, Grenoble, France, 27-29 September, 1988

Melvin A. Breuer, Gabrièle Saucier, Anthony Ambler, 1989 .

Logic Level Simulation

Melvin A. Breuer, Arthur D. Friedman, 1976 .

Functional Level Primitives in Test Generation

Melvin A. Breuer, Arthur D. Friedman, A. D. Friedman, 1980, IEEE Transactions on Computers.

Error Rate Estimation for Defective Circuits via Ones Counting

Melvin A. Breuer, Zhaoliang Pan, 2012, TODE.

Test program synthesis for modules and chips having boundary scan

Melvin A. Breuer, Jung-Cheun Lien, J. Lien, 1993, J. Electron. Test..

Estimating BIST Resources in High-level Synthesis

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1996 .

Test generation in VLSI circuits for crosstalk noise

Melvin A. Breuer, Sandeep K. Gupta, Weiyu Chen, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Reduction of detected acceptable faults for yield improvement via error-tolerance

Melvin A. Breuer, Kuen-Jong Lee, Tong-Yu Hsieh, 2007 .

A design flow to maximize yield/area of physical devices via redundancy

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2012, 2012 IEEE International Test Conference.

Concurrent Control of Multiple BIT

Melvin A. Breuer, Rajiv Gupta, Jung-Cheun Lien, 1988 .

Cbase 1.0: a CAD database for VLSI circuits using object oriented technology

Ellis Horowitz, Melvin A. Breuer, Rajiv Gupta, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Blade -- A Timing Violation Resilient Asynchronous Template

Melvin A. Breuer, Zhichao Li, Peter A. Beerel, 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.

State-of-the-Art Assessment of Testing and Testability of Custom LSI/VLSI Circuits. Volume IV. Test Generation.

Melvin A. Breuer, A. J. Carlan, 1982 .

Efficient Single-Layer Routing Along a Line of Points

Melvin A. Breuer, Harold W. Carter, 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Will 0.1um Digital Circuits Require Mixed-Signal Testing

Melvin A. Breuer, Bozena Kaminska, Donald L. Wheater, 1997, VTS.

Procedures ForEliminating Static andDynamic Hazards inTest Generation

Melvin A. Breuer, R. Loyd Harrison, 1974 .

Reorganizing circuits to aid testability

Melvin A. Breuer, Rajiv Gupta, Rajagopalan Srinivasan, 1991, IEEE Design & Test of Computers.

Digital system design automation : languages, simulation & data base

Melvin A. Breuer, M. H. MacDougall, 1975 .

Digital Systems Testing and Design for Testability

Melvin A. Breuer, Miron Abramovici, Allan D. Friedman, 1990 .

The Construction of Minimal Area Power and Ground Nets for VLSI Circuits

Melvin A. Breuer, Salim U. Chowdhury, 1985, 22nd ACM/IEEE Design Automation Conference.

Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors

Yue Gao, Melvin A. Breuer, Sandeep K. Gupta, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Crosstalk test generation on pseudo industrial circuits: a case study

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Combinatorial Equivalence of (0, 1) Circulant Matrices

Melvin A. Breuer, 1969, J. Comput. Syst. Sci..

Intelligible test techniques to support error-tolerance

Melvin A. Breuer, M. Breuer, 2004, 13th Asian Test Symposium.

On the charge sharing problem in CMOS stuck-open fault testing

Melvin A. Breuer, Kuen-Jong Lee, M. Breuer, 1990, Proceedings. International Test Conference 1990.

Blade - A Timing Violation Resilient Asynchronous Design Template

Melvin A. Breuer, Peter A. Beerel, Dylan Hand, 2014 .

Test Generation for Combinational Circuits

Melvin A. Breuer, Arthur D. Friedman, 1976 .

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1995, 32nd Design Automation Conference.

Incremental Processing Applied to Steinberg's Placement Procedure

Melvin A. Breuer, Harold W. Carter, Zahir A. Syed, 1979, 16th Design Automation Conference.

Switch-level delay test

Melvin A. Breuer, Sandeep K. Gupta, Suriyaprakash Natarajan, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2008, 2008 17th Asian Test Symposium.

General survey of design automation of digital computers

Melvin A. Breuer, M. Breuer, 1966 .

On Routing for Custom Integrated Circuits

Melvin A. Breuer, Abbas El Gamal, Zahir A. Syed, 1982, DAC 1982.

A methodology for custom VLSI layout

Melvin A. Breuer, A. Kumar, 1983 .

Control strategies for chip-based DFT/BIST hardware

Melvin A. Breuer, Massoud Pedram, Debaditya Mukherjee, 1994, Proceedings., International Test Conference.

Tolerance of performance degrading faults for effective yield improvement

Melvin A. Breuer, Sandeep K. Gupta, Kuen-Jong Lee, 2009, 2009 International Test Conference.

High quality robust tests for path delay faults

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Trading off area, yield and performance via hybrid redundancy in multi-core architectures

Yue Gao, Melvin A. Breuer, Da Cheng, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Computer hardware description languages and their applications : proceedings of the IFIP TC-10 Fifth International Conference on Computer Hardware Description Languages and Their Applications, Kaiserslautern, F.R.G., 7-9 September 1981

Melvin A. Breuer, Ifip Tc, Reiner Hartenstein, 1981 .

A KNOWLEDGE-BASED SYSTEM FOR

Melvin A. Breuer, Xi-an Zhu, 1988 .

Constraints for using IDDQ testing to detect CMOS bridging faults

Melvin A. Breuer, Kuen-Jong Lee, M. Breuer, 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

Introducing redundant computations in a behavior for reducing BIST resources

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Digital systems testing and testable design

Melvin A. Breuer, Arthur D. Friedman, A. D. Friedman, 1990 .

Coding the vertexes of a graph

Melvin A. Breuer, M. Breuer, 1966, IEEE Trans. Inf. Theory.

A systematic approach for designing testable VLSI circuits

Melvin A. Breuer, Charles Njinda, Sen-Pin Lin, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

A low cost BIST methodology and associated novel test pattern generator

Melvin A. Breuer, Sandeep K. Gupta, Sen-Pin Lin, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

XIDEN: crosstalk target identification framework

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2002, Proceedings. International Test Conference.

Process aggravated noise (PAN): new validation and test problems

Melvin A. Breuer, Sandeep K. Gupta, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Built-in test for folded programmable logic arrays

Melvin A. Breuer, F. Saheban, 1987, Microprocess. Microsystems.

An unexpected result in coding the vertices of a graph

Melvin A. Breuer, Jon Folkman, J. Folkman, 1967 .

Heuristic switching expression simplification

Melvin A. Breuer, M. Breuer, 1968, ACM National Conference.

A Universal Test Sequence for CMOS Scan

Melvin A. Breuer, Kuen-Jong Lee, M. Breuer, 1990 .

Self-diagnosis of regular arrays of processors

Melvin A. Breuer, Farhad Saheban, M. Breuer, 1992 .

Merging multiple FSM controllers for DFT/BIST hardware

Melvin A. Breuer, Massoud Pedram, Debaditya Mukherjee, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

AN ALGORITHM FOR GENERATING A FAULT DETECTION TEST FOR A CLASS OF SEQUENTIAL CIRCUITS

Melvin A. Breuer, 1971 .

An optimum testing algorithm for some symmetric coherent systems

Melvin A. Breuer, Salam Salloum, 1984 .

Ieee Vlsi Test Symposium

Melvin A. Breuer, Ching-Te Chuang, Edward J. McCluskey, 2011 .