Sandeep K. Gupta

发表

Efficient Scheduling of Path Delay Tests for Latch-Based Circuits

Sandeep K. Gupta, Kun Young Chung, 2009, 2009 27th IEEE VLSI Test Symposium.

Optimal Redundancy Designs for CNFET-Based Circuits

Sandeep K. Gupta, Fangzhou Wang, Da Cheng, 2014, 2014 IEEE 23rd Asian Test Symposium.

Design and test of latch-based circuits to maximize performance, yield, and delay test quality

Sandeep K. Gupta, Kun Young Chung, 2010, 2010 IEEE International Test Conference.

Test embedding with discrete logarithms

Melvin A. Breuer, Sandeep K. Gupta, Mody Lempel, 1994, Proceedings of IEEE VLSI Test Symposium.

A satisfiability-based test generator for path delay faults in combinational circuits

Sandeep K. Gupta, Chih-Ang Chen, 1996, DAC '96.

Asymmetric sizing: An effective design approach for SRAM cells against BTI aging

Sandeep K. Gupta, Xuan Zuo, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

A BIST methodology for comprehensive testing of RAM with reduced heat dissipation

Sandeep K. Gupta, Hugo Cheung, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

A systematic methodology to improve yield per area of highly-parallel CMPs

Sandeep K. Gupta, Da Cheng, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits

Sandeep K. Gupta, Yuan-Chieh Hsu, 1996, IEEE Trans. Computers.

New Validation and Test Problems for High Performance Deep Sub-micron VLSI Circuits

Melvin A. Breuer, Sandeep K. Gupta, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Test generation and embedding for built-in self-test

Sandeep K. Gupta, Chih-Ang Chen, 1996 .

Test generation for crosstalk-induced faults: framework and computational results

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation

Sandeep K. Gupta, Seongmoon Wang, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Facial Expression Recognition Using Gabor-Mean-DWT Feature Extraction Technique

Sandeep K. Gupta, Govardhan Mattela, S. Gupta, 2018, 2018 5th International Conference on Signal Processing and Integrated Networks (SPIN).

Exact fault simulation for systems on silicon that protects each core's intellectual property (IP)

Sandeep K. Gupta, Md. Saffat Quasem, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

A New March Test for Process-Variation Induced Delay Faults in SRAMs

Sandeep K. Gupta, Ramesh Govindan, Jia Zeng, 2013, 2013 22nd Asian Test Symposium.

Test generation for capacitance and inductance induced noise on interconnects in vlsi logic

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2006 .

ATPG for heat dissipation minimization during scan testing

Sandeep K. Gupta, Seongmoon Wang, 1997, DAC.

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2009, 2009 Asian Test Symposium.

FOTG: fault-oriented stress testing of IP multicast

Ahmed Helmy, Sandeep K. Gupta, A. Helmy, 2005, IEEE Communications Letters.

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms

Sandeep K. Gupta, Chih-Ang Chen, 1996, IEEE Trans. Computers.

BIST TPG for SRAM cluster interconnect testing at board level

Sandeep K. Gupta, Chen-Huan Chiang, 2000, Proceedings of the Ninth Asian Test Symposium.

An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems

Yue Gao, Sandeep K. Gupta, Massoud Pedram, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Multiple tests for each gate delay fault: higher coverage and lower test application cost

Melvin A. Breuer, Sandeep K. Gupta, Shahdad Irajpour, 2005, IEEE International Conference on Test, 2005..

A new framework for designing and analyzing BIST techniques: computation of exact aliasing probability

Dhiraj K. Pradhan, Sandeep K. Gupta, D. Pradhan, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

A new framework for static timing analysis, incremental timing refinement, and timing simulation

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

Trojan detection via delay measurements: A new approach to select paths and vectors to maximize effectiveness and minimize cost

Sandeep K. Gupta, Byeongju Cha, S. Gupta, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Bounds on pseudoexhaustive test lengths

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Novel test pattern generators for pseudo-exhaustive testing

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 1993, Proceedings of IEEE International Test Conference - (ITC).

Modeling and testing crosstalk faults in inter-core interconnects that include tri-state and bi-directional nets

Sandeep K. Gupta, Wichian Sirisaengtaksin, 2004, 13th Asian Test Symposium.

Validation and test generation for oscillatory noise in VLSI interconnects

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

An ATPG for threshold testing: obtaining acceptable yield in future processes

Sandeep K. Gupta, Zhigang Jiang, S. Gupta, 2002, Proceedings. International Test Conference.

Aliasing Probability for Multiple Input Signature Analyzer

Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky, 1990, IEEE Trans. Computers.

Switch-level delay test of domino logic circuits

Melvin A. Breuer, Sandeep K. Gupta, Suriyaprakash Natarajan, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

TA-PSV—Timing Analysis for Partially Specified Vectors

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2002, J. Electron. Test..

On Accelerating Path Delay Fault Simulation of Long Test Sequences

Sandeep K. Gupta, Yi-Shing Chang, Suriyaprakash Natarajan, 2008, 2008 IEEE International Test Conference.

LT-RTPG: a new test-per-scan BIST TPG for low switching activity

Sandeep K. Gupta, Seongmoon Wang, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

BIST TPG for Combinational Cluster Interconnect Testing at Board Level

Sandeep K. Gupta, Chen-Huan Chiang, 2000, J. Electron. Test..

Accurate modeling and fault simulation of Byzantine resistive bridges

Sandeep K. Gupta, Hugo Cheung, 2007, 2007 25th International Conference on Computer Design.

Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations

Sandeep K. Gupta, Ramesh Govindan, Bin Liu, 2013, 2013 22nd Asian Test Symposium.

An Electronic Programmer for an Integrator

Sandeep K. Gupta, 1982 .

Concurrent control of multiple BIT structures

Melvin A. Breuer, Sandeep K. Gupta, Jung-Cheun Lien, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems

Yue Gao, Sandeep K. Gupta, Massoud Pedram, 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Estimation of BIST Resources During High-Level Synthesis

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, J. Electron. Test..

BIST TPG for faults in system backplanes

Sandeep K. Gupta, Chen-Huan Chiang, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Fault-oriented Test Generation for Multicast Routing Protocol Design

Deborah Estrin, Ahmed Helmy, Sandeep K. Gupta, 1998, FORTE.

A Resizing Method to Minimize Effects of Hardware Trojans

Sandeep K. Gupta, Byeongju Cha, S. Gupta, 2014, 2014 IEEE 23rd Asian Test Symposium.

Test generation for path-delay faults in one-dimensional iterative logic arrays

Sandeep K. Gupta, Nabil M. Abdulrazzaq, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Systematic testing of protocol robustness: case studies on mobile IP and MARS

Ahmed Helmy, Sandeep K. Gupta, Shamim Begum, 2000, Proceedings 25th Annual IEEE Conference on Local Computer Networks. LCN 2000.

Efficient Trojan Detection via Calibration of Process Variations

Sandeep K. Gupta, Byeongju Cha, S. Gupta, 2012, 2012 IEEE 21st Asian Test Symposium.

Clock Grouping: A Low Cost DFT Methodology for Delay Testing

Sandeep K. Gupta, Wen-Chang Fang, 1994, 31st Design Automation Conference.

ERTG: A test generator for error-rate testing

Sandeep K. Gupta, Shideh Shahidi, S. Gupta, 2007, 2007 IEEE International Test Conference.

Design of efficient BIST test pattern generators for delay testing

Sandeep K. Gupta, Chih-Ang Chen, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A new circuit simplification method for error tolerant applications

Sandeep K. Gupta, Doochul Shin, S. Gupta, 2011, 2011 Design, Automation & Test in Europe.

The STRESS method for boundary-point performance analysis of end-to-end multicast timer-suppression mechanisms

Deborah Estrin, Ahmed Helmy, Sandeep K. Gupta, 2002, IEEE/ACM Transactions on Networking.

Making the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment More Space Efficient in Practice (Extended Abstract)

Sandeep K. Gupta, Alejandro A. Schäffer, John D. Kececioglu, 1995, CPM.

Test generation for crosstalk-induced delay in integrated circuits

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Modeling and simulation for crosstalk aggravated by weak-bridge defects between on-chip interconnects

Melvin A. Breuer, Sandeep K. Gupta, Lei Wang, 2004, 13th Asian Test Symposium.

Threshold Testing: Improving Yield for Nanoscale VLSI

Sandeep K. Gupta, Zhigang Jiang, S. Gupta, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Threshold testing: Covering bridging and other realistic faults

Sandeep K. Gupta, Zhigang Jiang, S. Gupta, 2005, 14th Asian Test Symposium (ATS'05).

Analytical models for crosstalk excitation and propagation in VLSI circuits

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Zero Aliasing for Modeled Faults

Sandeep K. Gupta, Mody Lempel, S. Gupta, 1995, IEEE Trans. Computers.

Data Path Allocation Techniques for High-level Synthesis of Low BIST Area Overhead Designs

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 2007 .

Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits

Sandeep K. Gupta, Prasanjeet Das, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

Analysis and optimization of soft error tolerance strategies for real-time systems

Yue Gao, Sandeep K. Gupta, Bowen Zheng, 2015, 2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

SRAM Array Yield Estimation under Spatially-Correlated Process Variation

Sandeep K. Gupta, Jizhe Zhang, 2014, 2014 IEEE 23rd Asian Test Symposium.

Designing multiple scan chains for systems-on-chip

Sandeep K. Gupta, Md. Saffat Quasem, 2003, 2003 Test Symposium.

A methodology for transforming memory tests for in-system testing of direct mapped cache tags

Sandeep K. Gupta, Sultan M. Al-Harbi, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Analysis of ground bounce in deep sub-micron circuits

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 1993, 30th ACM/IEEE Design Automation Conference.

Process variations and their impact on circuit operation

Melvin A. Breuer, Sandeep K. Gupta, Suriyaprakash Natarajan, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

A methodology to design efficient BIST test pattern generators

Sandeep K. Gupta, Chih-Ang Chen, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Structural delay testing of latch-based high-speed pipelines with time borrowing

Sandeep K. Gupta, Kun Young Chung, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Low-cost scan-based delay testing of latch-based circuits with time borrowing

Sandeep K. Gupta, Kun Young Chung, 2006, 24th IEEE VLSI Test Symposium.

Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model

Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky, 1991, 1991, Proceedings. International Test Conference.

Efficient identification of crosstalk induced slowdown targets

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2004, 13th Asian Test Symposium.

A new gate delay model for simultaneous switching and its applications

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2001, DAC '01.

Using hardware testing approaches to improve software testing: Undetectable mutant identification

Sandeep K. Gupta, Jianwei Zhang, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Improving the Practical Space and Time Efficiency of the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment

Sandeep K. Gupta, Alejandro A. Schäffer, John D. Kececioglu, 1995, J. Comput. Biol..

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Melvin A. Breuer, Sandeep K. Gupta, Wei-Yu Chen, 2002, J. Electron. Test..

Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning

Sandeep K. Gupta, Prasanjeet Das, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

A multi-layered methodology for defect-tolerance of datapath modules in processors

Sandeep K. Gupta, Hsunwei Hsiung, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

BIST TPG for combinational cluster (glue logic) interconnect testing at board level

Sandeep K. Gupta, Chen-Huan Chiang, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Allocation Techniques for Reducing BIST Area Overhead of Data Paths

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, J. Electron. Test..

Test generation for ground bounce in internal logic circuitry

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Path delay fault diagnosis in combinational circuits with implicitfault enumeration

Abhijit Chatterjee, Sandeep K. Gupta, Yuan-Chieh Hsu, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test generation for maximizing ground bounce for internal circuitry with reconvergent fan-outs

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects

Sandeep K. Gupta, Wichian Sirisaengtaksin, 2005, 14th Asian Test Symposium (ATS'05).

Approximate logic synthesis for error tolerant applications

Sandeep K. Gupta, Doochul Shin, S. Gupta, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

An efficient methodology for generating optimal and uniform march tests

Sandeep K. Gupta, Sultan M. Al-Harbi, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Analyzing crosstalk in the presence of weak bridge defects

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

STAX: Statistical Crosstalk Target Set Compaction

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Characterization of granularity and redundancy for SRAMs for optimal yield-per-area

Sandeep K. Gupta, Jae Chul Cha, 2008, 2008 IEEE International Conference on Computer Design.

Test embedding with discrete logarithms

Melvin A. Breuer, Sandeep K. Gupta, Mody Lempel, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging

Sandeep K. Gupta, Jizhe Zhang, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Path-delay fault simulation for circuits with large numbers of paths for very large test sets

Sandeep K. Gupta, Nabil M. Abdulrazzaq, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Yield estimation and statistical design of memristor cross-point memory systems

Sandeep K. Gupta, Jizhe Zhang, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

Scheduling and module assignment for reducing BIST resources

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, Proceedings Design, Automation and Test in Europe.

Optimizing redundancy design for chip-multiprocessors for flexible utility functions

Sandeep K. Gupta, Da Cheng, 2013, Proceedings of the 2013 25th International Teletraffic Congress (ITC).

PPB: Partially-working processors binning for maximizing wafer utilization

Sandeep K. Gupta, Da Cheng, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression

Dhiraj K. Pradhan, Sandeep K. Gupta, D. Pradhan, 1991, IEEE Trans. Computers.

A Re-design Technique for Datapath Modules in Error Tolerant Applications

Sandeep K. Gupta, Doochul Shin, S. Gupta, 2008, 2008 17th Asian Test Symposium.

Zero aliasing compression

Dhiraj K. Pradhan, Sudhakar M. Reddy, Sandeep K. Gupta, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

Modeling and test generation for worst-case performance evaluation of MAC protocols for wireless ad hoc networks

Ahmed Helmy, Sandeep K. Gupta, Shamim Begum, 2009, 2009 IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems.

Defect and error tolerance in the presence of massive numbers of defects

Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak, 2004, IEEE Design & Test of Computers.

Performance Analysis of Wireless MAC Protocols Using a Search Based Framework

Ahmed Helmy, Sandeep K. Gupta, Shamim Begum, 2007, 2007 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems.

Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Benefits of a SoC-specific test methodology

Sandeep K. Gupta, Md. Saffat Quasem, Zhigang Jiang, 2003, IEEE Design & Test of Computers.

Test generation for maximizing ground bounce considering circuit delay

Melvin A. Breuer, Sandeep K. Gupta, Yi-Shing Chang, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Systematic Performance Evaluation of Multipoint Protocols

Deborah Estrin, Ahmed Helmy, Sandeep K. Gupta, 2000, FORTE.

Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture

Sandeep K. Gupta, Jae Chul Cha, 2008, 2008 International Symposium on Parallel and Distributed Computing.

DS-LFSR: a new BIST TPG for low heat dissipation

Sandeep K. Gupta, Seongmoon Wang, S. Gupta, 1997, Proceedings International Test Conference 1997.

An automatic test pattern generator for at-speed robust path delay testing

Sandeep K. Gupta, Yuan-Chieh Hsu, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Analytic models for crosstalk delay and pulse analysis under non-ideal inputs

Melvin A. Breuer, Sandeep K. Gupta, Weiyu Chen, 1997, Proceedings International Test Conference 1997.

Systematic testing of multicast routing protocols: analysis of forward and backward search techniques

Deborah Estrin, Ahmed Helmy, Sandeep K. Gupta, 2000, Proceedings Ninth International Conference on Computer Communications and Networks (Cat.No.00EX440).

Introducing redundant computations in RTL data paths for reducing BIST resources

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 2001, TODE.

BIST TPGs for faults in board level interconnect via boundary scan

Sandeep K. Gupta, Chen-Huan Chiang, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

On Generating Vectors for Accurate Post-Silicon Delay Characterization

Sandeep K. Gupta, Prasanjeet Das, 2011, 2011 Asian Test Symposium.

Selection of Paths for Delay Testing

Sandeep K. Gupta, I-De Huang, 2005, 14th Asian Test Symposium (ATS'05).

Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa

Dhiraj K. Pradhan, Sandeep K. Gupta, 1996, IEEE Trans. Computers.

HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2010, 2010 19th IEEE Asian Test Symposium.

Efficient BIST TPG design and test set compaction via input reduction

Sandeep K. Gupta, Chih-Ang Chen, S. Gupta, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Delay Fault Testing: How Robust are Our Models?

Sudhakar M. Reddy, Sandeep K. Gupta, Prab Varma, 1996, VTS.

Efficient post-silicon validation via segmentation of process variation envelope — Global vs local variations

Sandeep K. Gupta, Prasanjeet Das, 2014, Fifteenth International Symposium on Quality Electronic Design.

Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models

Melvin A. Breuer, Sandeep K. Gupta, Shahdad Irajpour, 2004, 2004 International Conferce on Test.

A framework to minimize test escape and yield loss during I/sub DDQ/ testing: a case study

Sandeep K. Gupta, Hugo Cheung, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Weighted random robust path delay testing of synthesized multilevel circuits

Sandeep K. Gupta, Weili Wang, 1994, Proceedings of IEEE VLSI Test Symposium.

An enhanced test generator for capacitance induced crosstalk delay faults

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2003, 2003 Test Symposium.

Modeling the interactions between MAC and higher layer: A systematic approach to generate high-level scenarios from MAC-layer scenarios

Ahmed Helmy, Sandeep K. Gupta, Shamim Begum, 2010, TOMC.

Novel Test Pattern Generators for Pseudoexhaustive Testing

Melvin A. Breuer, Sandeep K. Gupta, Rajagopalan Srinivasan, 2000, IEEE Trans. Computers.

A test generation approach for systems-on-chip that use intellectual property cores

Sandeep K. Gupta, Zhigang Jiang, 2003, 2003 Test Symposium.

Lower bounds on test resources for scheduled data flow graphs

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1996, DAC '96.

Matrix Inversion on a PIM (Processor-in-Memory)

Sandeep K. Gupta, Jae Chul Cha, 2008, 2008 International Conference on Computer Science and Software Engineering.

An automatic test pattern generator for minimizing switching activity during scan testing activity

Sandeep K. Gupta, Seongmoon Wang, S. Gupta, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

BIST test pattern generators for stuck-open and delay testing

Sandeep K. Gupta, Chih-Ang Chen, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Salvaging chips with caches beyond repair

Sandeep K. Gupta, Hsunwei Hsiung, Byeongju Cha, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Estimating BIST Resources in High-level Synthesis

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1996 .

Test generation in VLSI circuits for crosstalk noise

Melvin A. Breuer, Sandeep K. Gupta, Weiyu Chen, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

A design flow to maximize yield/area of physical devices via redundancy

Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, 2012, 2012 IEEE International Test Conference.

Body Area Networking: Technology and Applications

Romano Fantacci, Joseph A. Paradiso, Sandeep K. Gupta, 2009, IEEE J. Sel. Areas Commun..

A framework for systematic evaluation of multicast congestion control protocols

Ahmed Helmy, Sandeep K. Gupta, Karim Seada, 2004, IEEE Journal on Selected Areas in Communications.

Generating complete and optimal march tests for linked faults in memories

Sandeep K. Gupta, Sultan M. Al-Harbi, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

ATPG for heat dissipation minimization during test application

Sandeep K. Gupta, Seongmoon Wang, S. Gupta, 1994, Proceedings., International Test Conference.

Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates

Sandeep K. Gupta, Jae Chul Cha, S. Gupta, 2011, 2011 Asian Test Symposium.

Random pattern testable logic synthesis

Sandeep K. Gupta, Chen-Huan Chiang, 1994, ICCAD.

Process variation oriented delay testing of SRAMs

Sandeep K. Gupta, Xuan Zuo, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors

Yue Gao, Melvin A. Breuer, Sandeep K. Gupta, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Crosstalk test generation on pseudo industrial circuits: a case study

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy

Sandeep K. Gupta, Da Cheng, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ATPG for Heat Dissipation Minimization During Test Application

Sandeep K. Gupta, Seongmoon Wang, 1998, IEEE Trans. Computers.

A new path-oriented effect-cause methodology to diagnose delay failures

Sandeep K. Gupta, Yuan-Chieh Hsu, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1995, 32nd Design Automation Conference.

SRAM yield-per-area optimization under spatially-correlated process variation

Sandeep K. Gupta, Jizhe Zhang, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

Switch-level delay test

Melvin A. Breuer, Sandeep K. Gupta, Suriyaprakash Natarajan, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults

Melvin A. Breuer, Sandeep K. Gupta, Arani Sinha, 2008, 2008 17th Asian Test Symposium.

Towards systematic roadmaps for networked systems

Sandeep K. Gupta, Ramesh Govindan, Bin Liu, 2012, HotNets-XI.

Tolerance of performance degrading faults for effective yield improvement

Melvin A. Breuer, Sandeep K. Gupta, Kuen-Jong Lee, 2009, 2009 International Test Conference.

TCP vs. TCP: a systematic study of adverse impact of short-lived TCP flows on long-lived TCP flows

Sandeep K. Gupta, Ahmed Helmy, S. Ebrahimi-Taghizadeh, 2005, Proceedings IEEE 24th Annual Joint Conference of the IEEE Computer and Communications Societies..

High quality robust tests for path delay faults

Melvin A. Breuer, Sandeep K. Gupta, Liang-Chi Chen, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

AVM: application-level virtual memory

Sandeep K. Gupta, Dawson R. Engler, M. Frans Kaashoek, 1995, Proceedings 5th Workshop on Hot Topics in Operating Systems (HotOS-V).

Recent advances in BIST

Sandeep K. Gupta, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

An Industrial Case Study of Sticky Path-Delay Faults

Sandeep K. Gupta, Sreejit Chakravarty, Yi-Shing Chang, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation

Sandeep K. Gupta, Jean-Luc Gaudiot, Jung-Yup Kang, 2008, IEEE Transactions on Computers.

DS-LFSR: a BIST TPG for low switching activity

Sandeep K. Gupta, Seongmoon Wang, S. Gupta, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Designing reconfigurable multiple scan chains for systems-on-chip

Sandeep K. Gupta, Md. Saffat Quasem, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Introducing redundant computations in a behavior for reducing BIST resources

Melvin A. Breuer, Sandeep K. Gupta, Ishwar Parulkar, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A novel software-based defect-tolerance approach for application-specific embedded systems

Sandeep K. Gupta, Da Cheng, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

A low cost BIST methodology and associated novel test pattern generator

Melvin A. Breuer, Sandeep K. Gupta, Sen-Pin Lin, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

XIDEN: crosstalk target identification framework

Shahin Nazarian, Melvin A. Breuer, Sandeep K. Gupta, 2002, Proceedings. International Test Conference.

Estimating Error Rate during Self-Test via One's Counting

Sandeep K. Gupta, Shideh Shahidi, S. Gupta, 2006, 2006 IEEE International Test Conference.

Process aggravated noise (PAN): new validation and test problems

Melvin A. Breuer, Sandeep K. Gupta, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology

Sandeep K. Gupta, Wichian Sirisaengtaksin, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..