Rajesh Reddy Tummuru

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Subramanian S. Iyer, Toshiaki Kirihata, Donald W. Plass, 2016, IEEE Journal of Solid-State Circuits.

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

Ming Yin, Balaji Jayaraman, Subramanian S. Iyer, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

Ming Yin, Balaji Jayaraman, Subramanian S. Iyer, 2018, IEEE Journal of Solid-State Circuits.