Alberto Cestero

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Subramanian S. Iyer, Toshiaki Kirihata, Donald W. Plass, 2016, IEEE Journal of Solid-State Circuits.

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

Subramanian S. Iyer, Srivatsan Chellappa, Toshiaki Kirihata, 2013, IEEE Journal of Solid-State Circuits.

Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM

Subramanian S. Iyer, Toshiaki Kirihata, Alberto Cestero, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

Xiang Chen, Subramanian S. Iyer, Toshiaki Kirihata, 2007, 2007 IEEE Custom Integrated Circuits Conference.

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

Ming Yin, Balaji Jayaraman, Subramanian S. Iyer, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

3Di DC-DC Buck Micro Converter with TSVs, Grind Side Inductors, and Deep Trench Decoupling Capacitors in 32nm SOI CMOS

Alberto Cestero, Sami Rosenblatt, Gary Maier, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Subramanian S. Iyer, Toshiaki Kirihata, Alberto Cestero, 2013, IEEE Journal of Solid-State Circuits.

14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing

Toshiaki Kirihata, Faraz Khan, Liu Jiang, 2018, IEEE Solid-State Circuits Letters.

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

Ming Yin, Balaji Jayaraman, Subramanian S. Iyer, 2018, IEEE Journal of Solid-State Circuits.