B.J. Park

An outstanding and highly manufacturable 80nm DRAM technology

J.W. Lee, H.J. Kim, Kinam Kim, 2003, IEEE International Electron Devices Meeting 2003.

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

H.J. Kim, Kinam Kim, H.S. Kim, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM

B.J. Park, K.N. Kim, H.S. Jeong, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

H.J. Kim, Kinam Kim, Y.S. Lee, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generations

Y.S. Hwang, B.J. Park, Y.S. Chun, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

Y.S. Hwang, B.J. Park, K.N. Kim, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A 0.13 /spl mu/m logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 /spl mu/m generation

B.J. Park, D. Shum, J. Liu, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A novel robust TiN/AHO/TiN capacitor and CoSi/sub 2/ cell pad structure for 70nm stand-alone and embedded DRAM technology and beyond

H.S. Kim, J.M. Park, Y.S. Hwang, 2002, Digest. International Electron Devices Meeting,.

A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

Y.S. Lee, J.M. Park, Y.S. Hwang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..