Hisakatsu Yamaguchi

发表

A 24-Gb/s source-series terminated driver with inductor peaking in 28-nm CMOS

Takuji Yamamoto, Hirotaka Tamura, Yasumoto Tomita, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

Hirotaka Tamura, Masaya Kibune, Junji Ogawa, 2010, IEEE Journal of Solid-State Circuits.

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

Takushi Hashida, Yoichi Koyanagi, Hirotaka Tamura, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

18-GHz Clock Distribution Using a Coupled VCO Array

Takayuki Shibasaki, Hirotaka Tamura, Tadahiro Kuroda, 2007, IEICE Trans. Electron..

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance

Hirotaka Tamura, Ali Sheikholeslami, Joshua Liang, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Event-Driven Model for High Speed End-to-End Simulations of Transmission System with Non-Linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits

Hisakatsu Yamaguchi, Jun Matsui, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR

Hirotaka Tamura, Ali Sheikholeslami, Joshua Liang, 2018, IEEE Journal of Solid-State Circuits.

Circuits for CMOS High-Speed I/O in Sub-100nm Technologies (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)

Masaya Kibune, Junji Ogawa, Hisakatsu Yamaguchi, 2006 .

Jitter injection for on-chip jitter measurement in PI-based CDRs

Hirotaka Tamura, Ali Sheikholeslami, Joshua Liang, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Hirotaka Tamura, Ali Sheikholeslami, Joshua Liang, 2018, IEEE Journal of Solid-State Circuits.

A 0.12mm2 5Gbps receiver with a level shifting equalizer and a cumulative-histogram-based adaptation engine

Takuji Yamamoto, Hirotaka Tamura, Yasumoto Tomita, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

F6: Energy-efficient I/O design for next-generation systems

Chulwoo Kim, Elad Alon, Frank O'Mahony, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI

Hirotaka Tamura, William W. Walker, Marcus van Ierssel, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process

Yoshiyasu Doi, Hirotaka Tamura, Junji Ogawa, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

Takayuki Shibasaki, Takumi Danjo, Hiroki Miyaoka, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

10–40 Gb/s I/O design for data communications

Anthony Chan Carusone, Ken Chang, Ali Sheikholeslami, 2012, 2012 IEEE International Solid-State Circuits Conference.

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies

Hirotaka Tamura, Kouichi Kanda, Masaya Kibune, 2006, IEICE Trans. Electron..

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

Yoshiyasu Doi, Hirotaka Tamura, Masaya Kibune, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Session 26 overview: Energy-efficient dense interconnects: Wireline subcommittee

SeongHwan Cho, Hisakatsu Yamaguchi, 2014 .

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS

Takuji Yamamoto, Hirotaka Tamura, Masaya Kibune, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Session 2 overview: Ultra-high-speed transceivers and equalizers

Ken Chang, Hisakatsu Yamaguchi, Ken Chang, 2013, IEEE International Solid-State Circuits Conference.

F3: Emerging technologies for wireline communication

Tadahiro Kuroda, Elad Alon, Azita Emami-Neyestanak, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS

Takayuki Shibasaki, Hirotaka Tamura, Wahid Rahman, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

Takayuki Shibasaki, Hirotaka Tamura, Ali Sheikholeslami, 2017, IEEE Journal of Solid-State Circuits.

Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management

Atsushi Ike, Katsuhiro Yoda, Hisakatsu Yamaguchi, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An 8-to-16GHz 28nm CMOS clock distribution circuit based on mutual-injection-locked ring oscillators

Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, 2013, 2013 Symposium on VLSI Circuits.