Yitao Ma

发表

Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application

Tao Li, Yitao Ma, Tetsuo Endoh, 2020, IEEE Access.

An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications

Tadashi Shibata, Yitao Ma, Tetsuo Endoh, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2016 .

A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate

Tao Li, Yitao Ma, Tetsuo Endoh, 2020, IEEE Access.

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Yitao Ma, Takahiro Hanyu, Masaaki Niwa, 2020, IEEE Journal of Solid-State Circuits.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2017 .

Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm (Special Issue : Solid State Devices and Materials)

Yitao Ma, Hongbo Zhu, Zuoxun Hou, 2013 .

12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems

Yitao Ma, Tadashi Shibata, 2010 .

A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching

Tadashi Shibata, Yitao Ma, Tetsuo Endoh, 2011, 2011 International SoC Design Conference.

A 47.14- $\mu\text{W}$ 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, IEEE Journal of Solid-State Circuits.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2016, Proceedings of the IEEE.

A 600-μW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing Magnetic Tunnel Junction (MTJ) Based Nonvolatile Memories with Novel Intelligent Power-Gating (IPG) Scheme

Yitao Ma, Tetsuo Endoh, Takahiro Hanyu, 2015 .

A free-extendible and ultralow-power nonvolatile multi-core associative coprocessor based on MRAM with inter-core pipeline scheme for large-scale full-adaptive nearest pattern searching

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2020, Japanese Journal of Applied Physics.

Highly accurate and efficient cluster validation index engine using global separation and local dispersion architecture for adaptive image clustering systems

Yitao Ma, Tetsuo Endoh, Hui Shen, 2021 .

Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT

Yitao Ma, Tetsuo Endoh, Ko Yoshikawa, 2022, IEEE Transactions on Industrial Informatics.