Shu-Shin Chin

发表

Extensible supply voltage control mechanism for low power array structure design

Sangjin Hong, Shu-Shin Chin, 2005, IEEE Trans. Circuits Syst. II Express Briefs.

Rapidly reconfigurable coarse-grained FPGA architecture for digital filtering applications

Sangjin Hong, Wei Wu, Shu-Shin Chin, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters

Petar M. Djuric, Sangjin Hong, Miodrag Bolic, 2006, J. VLSI Signal Process..

Multiplier architecture power consumption characterization for low-power DSP applications

Suhwan Kim, Sangjin Hong, Shu-Shin Chin, 2002, 9th International Conference on Electronics, Circuits and Systems.

A high-speed multi-port data buffer design for low-energy DSP applications

Sangjin Hong, Shu-Shin Chin, Fanshi Zhao, 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

Incorporating power reduction mechanism in arithmetic core design

Sangjin Hong, Shu-Shin Chin, 2004, IEEE Computer Society Annual Symposium on VLSI.

Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

Sangjin Hong, Shu-Shin Chin, 2003 .

Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization

Suhwan Kim, Sangjin Hong, Wei Hwang, 2004, J. VLSI Signal Process..

Variable-rate pipelined multiplier design for reconfigurable DSP applications

Sangjin Hong, Shu-Shin Chin, C. Connaway, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

Usage of application-specific switching activity for energy minimization of arithmetic units

Suhwan Kim, Sangjin Hong, Shu-Shin Chin, 2004, IEEE Computer Society Annual Symposium on VLSI.

Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications

Sangjin Hong, Shu-Shin Chin, 2005, J. VLSI Signal Process..

A coarse-grained FPGA architecture for reconfigurable baseband modulator/demodulator

Sangjin Hong, Shu-Shin Chin, Wei Wu, 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

A flexible resampling mechanism for parallel particle filters

Sangjin Hong, Shu-Shin Chin, S. Magesh, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Glitching power reduction through supply voltage adaptation mechanism for low power array structure design

Sangjin Hong, Shu-Shin Chin, Magesh Sadasivam, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).