Hideki Asai

发表

HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines

Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Nonlinear block latency insertion method for fast simulation of strongly coupled network with CMOS inverters

Tadatoshi Sekine, Hideki Asai, Yusuke Hizawa, 2011, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach

Hideki Asai, Yuya Nakazono, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Enhanced Time-Domain Circuit Simulation Technique Based on LIM

Hideki Asai, Yuichi Tanji, Hidemasa Kubota, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Ceramic based ozonizer for high speed sterilization

Kazuhiro Ishida, Hideki Asai, Shogo Masuda, 1988 .

Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits

Hideki Asai, Hidemasa Kubota, Takayuki Watanabe, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Efficient electromagnetic simulation of angled interconnection pattern by conformal- and HIE-FDTD methods

Hideki Asai, Hideaki Muraoka, Masaki Unno, 2011, 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

A Fast Neural Network Simulator for State Transition Analysis (Special Section on Nonlinear Theory and Its Applications)

Hideki Asai, A. Kamo, Teru Yoneyama, 1999 .

Acceleration techniques for the circuit simulation in the frequency domain

Hideki Asai, Hiroaki Makino, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Design and implementation of neuro-based discrete Walsh transform processor

Hideki Asai, T. Kamio, Hiroshi Ninomiya, 1996, Proceedings of International Conference on Neural Networks (ICNN'96).

Foreword

Hideki Asai, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Three-dimensional iterative electrical-thermal co-simulation (3-D IETC) method for power/thermal integrity analysis

Tadatoshi Sekine, Hideki Asai, Yasuhiro Nakatani, 2016, 2016 IEEE CPMT Symposium Japan (ICSJ).

Hierarchical decomposition system and its availability for network solution

Masakatsu Nishigaki, Hideki Asai, Nobuyuki Tanaka, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

Fast transient analysis of power/ground planes based on multi-rate locally implicit latency insertion method

Tadatoshi Sekine, Hideki Asai, Takaaki Hojo, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

An Alternating Implicit Block Overlapped FDTD (AIBO-FDTD) Method and Its Parallel Implementation

Hideki Asai, A. Kamo, Pornanong Pongpaibool, 2001 .

Fast transient simulation of power distribution network based on stabilized explicit method

Tadatoshi Sekine, Hideki Asai, Kaoru Nakagaki, 2015, 2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC).

Dynamically Overlapped Partitioning Technique to Implement Waveform Relaxation Simulation of Bipolar Circuits

Hideki Asai, Bandi Vijaya Gopal, 1993 .

Waveform relaxation method with dynamic partitioning technique for bipolar transistor circuits

Masakatsu Nishigaki, Hideki Asai, Koichi Hayashi, 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

Hybrid reduction technique for efficient simulation of linear/nonlinear mixed circuits

Hideki Asai, Hidemasa Kubota, Takayuki Watanabe, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Modeling of power distribution networks with signal lines for SPICE simulators

Hideki Asai, Takayuki Watanabe, 2005, 2005 IEEE International Symposium on Circuits and Systems.

GPU-Based Massively Parallel 3-D HIE-FDTD Method for High-Speed Electromagnetic Field Simulation

Hideki Asai, Masaki Unno, Shuichi Aono, 2012, IEEE Transactions on Electromagnetic Compatibility.

A neuro-based optimization algorithm for tiling problems with rotation

Hideki Asai, Shinsuke Manabe, 1999, IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339).

Optimum implementation of a locally implicit leapfrog scheme for fast simulation of inhomogeneously-meshed plane structures

Tadatoshi Sekine, Hideki Asai, 2013, 2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems.

Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method

Hideki Asai, Takayuki Watanabe, Atsushi Kamo, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Introduction to the special issue on “High performance analog circuits and design methodologies”

Hideki Asai, Luong Mo Dang, 2015 .

Relaxation-Based Algorithms for Bipolar Circuit Analysis

Masaki Ishida, Hideki Asai, Koichi Hayashi, 1993 .

Acceleration Techniques for Waveform Relaxation Approaches to Coupled Lossy Transmission Lines Circuit Analysis Using GMC and GLDW Techniques (Special Section on Nonlinear Theory and its Applications)

Hideki Asai, Takayuki Watanabe, 1996 .

CMOS circuit simulation using Latency Insertion Method

Tadatoshi Sekine, Hideki Asai, 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

Mixed mode circuit simulator SPLIT2.1 using dynamic network separation and selective trace

Masakatsu Nishigaki, Hideki Asai, Nobuyuki Tanaka, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Dedicated parallel Processor SMASH for Sparse LU Decomposition

Hideki Asai, Nobuyuki Tanaka, 1990 .

Invited Paper Three-Dimensional Module Packing Using 3DBSG Structure

Hideki Asai, Hiroshi Ninomiya, Hirokazu Yamagishi, 2005 .

A Positive Floating Resistor and A Negative Floating Resistor for the Analog Neural Network Implementation

Hideki Asai, Teru Yoneyama, Shashidhar Tantry, 2000 .

A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method

Hideki Asai, S. Indrapriyadarsini, Hiroshi Ninomiya, 2019, 2019 18th IEEE International Conference On Machine Learning And Applications (ICMLA).

New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data

Hideki Asai, Yuichi Tanji, Takayuki Watanabe, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Hybrid simulation of ESD events by SPICE-like and finite-difference time-domain methods

Tsuyoshi Takada, Tadatoshi Sekine, Hideki Asai, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

Neuro-Based Optimization Algorithm for Cubic Puzzles

Hideki Asai, Hiroyuki Yamamoto, Hiroshi Ninomiya, 1996 .

Multi-Rate Latency insertion MethodfortheFastTransient Simulation ofLargeNetworks withNonlinear iermination

Hideki Asai, Noritake Tsuboi, 2006 .

Optimization Method for the positions of Decoupling Capacitors on Printed Circuit Board using Krylov-subspace Technique

Hideki Asai, A. Kamo, Takayuki Watanabe, 2000 .

Orthogonalized steepest descent method for solving nonlinear equations

Hideki Asai, Hiroshi Ninomiya, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

A stabilized leapfrog scheme for circuit-based analysis of power delivery network

Tadatoshi Sekine, Hideki Asai, 2015, 2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS).

Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation

Hideki Asai, Hiroshi Ninomiya, Kimihiko Numayama, 2006, 2006 IEEE International Conference on Evolutionary Computation.

Iterative latency insertion method for large networks with low latency

Tadatoshi Sekine, Hideki Asai, 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.

Present status and future trend of power/signal integrity problems in chip/package/board codesign (Special issue on nonlinear circuits and signal processing)

Hideki Asai, 2007 .

Neuro-Based Optimization for Tiling Problem

Hideki Asai, Hiroshi Ninomiya, Takeshi Nakayama, 1994 .

Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation

Hideki Asai, Takayuki Watanabe, H. Asai, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Sparsely Interconnected Neural Networks for Associative Memories Applying Discrete Walsh Transform (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)

Hideki Asai, Takeshi Kamio, 1999 .

Locally Implicit Block-Type Leapfrog Scheme for Fast Transient Analysis of Multilayered Power Distribution Networks

Tadatoshi Sekine, Hideki Asai, Shingo Okada, 2015 .

Discrete Walsh transform processor based on Hopfield neural network

Hideki Asai, T. Kamio, Hiroshi Ninomiya, 1995, Proceedings of 1995 IEEE Instrumentation and Measurement Technology Conference - IMTC '95.

Generalized leapfrog scheme for large-scale circuit simulation

Tadatoshi Sekine, Hideki Asai, 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.

Analysis of PCB interconnects using electromagnetic reduction technique

Hideki Asai, Takayuki Watanabe, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit

Hideki Asai, Takanori Uno, Yuji Okazaki, 2010, IEICE Trans. Electron..

Large-Scale, High-Speed and High-Precision Simulation Method for the Multi-domain/Multi-scale Electronic System

Hideki Asai, Shingo Okada, Yuta Inoue, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Simulation of multiconductor transmission lines using block-latency insertion method and model order reduction technique

Tadatoshi Sekine, Hideki Asai, 2011, 2011 8th Workshop on Electromagnetic Compatibility of Integrated Circuits.

A framework for the simulation of electrostatic discharge immunity using the unified circuit modeling technique

Tadatoshi Sekine, Hideki Asai, 2013, 2013 IEEE International Symposium on Electromagnetic Compatibility.

Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow

Hideki Asai, S. Indrapriyadarsini, Hiroshi Ninomiya, 2018, 2018 17th IEEE International Conference on Machine Learning and Applications (ICMLA).

An optimization method for placement of decoupling capacitors on printed circuit board

Hideki Asai, A. Kamo, Takayuki Watanabe, 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

A floating resistor with positive and negative resistance operating at lower supply voltages

Hideki Asai, Teru Yoneyama, Shashidhar Tantry, 2002 .

A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient pdf

Hideki Asai, S. Indrapriyadarsini, Hiroshi Ninomiya, 2019, ECML/PKDD.

Acceleration Techniques for Waveform Relaxation Analysis of RLCG Transmission Lines Driven by Bipolar Logic Gates

Hideki Asai, Vijaya Gopal Bandi, 1993 .

High-speed interconnect simulation using MIMO type of adaptive least square method

Hideki Asai, Takayuki Watanabe, Atsushi Kamo, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network

Hideki Asai, Takeshi Kamio, Masahiro Yoshida, 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm

Hideki Asai, Yuichi Tanji, Hidemasa Kubota, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation

Hideki Asai, Yuichi Tanji, Hidemasa Kubota, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Multi-GPU HIE-FDTD method for the solution of large scale electromagnetic problems

Hideki Asai, Yuta Inoue, H. Asai, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A

Hideki Asai, Takafumi Yamamoto, Tsutomu Suzuki, 2006, IEEE Custom Integrated Circuits Conference 2006.

Acceleration techniques for Transient Simulation of Lossy Interconnects based on Waveform Relaxation Approach

Hideki Asai, Vijaya Gopal Bandi, 1994 .

Generalization of the Time-Domain Circuit Simulation Technique based on LIM

Hideki Asai, Yuichi Tanji, Takayuki Watanabe, 2005 .

Efficient PDN simulation by locally implicit latency insertion method based on rectangular meshes

Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

Neuro-based human-face recognition with 2-dimensional discrete Walsh transform

Masahiro Yoshida, Hideki Asai, Takeshi Kamio, 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium.

Comparison between latency insertion method (LIM) and relaxation method in thermal integrity analysis

Tadatoshi Sekine, Hideki Asai, Kazuki Sakamoto, 2015, 2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC).

Multi-GPU based fast electromagnetic simulation method for analysing PCB

Hideki Asai, Yuta Inoue, 2017, 2017 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC).

Mixed Mode Circuit Simulation Using Dynamic Network Separation and Selective Trace (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)

Masakatsu Nishigaki, Hideki Asai, Nobuyuki Tanaka, 1994 .

A Neural Net Approach to Discrete Walsh Transform (Special Section of Letters Selected from the 1994 IEICE Spring Conference)

Hideki Asai, Hiroshi Ninomiya, Takashi Kamio, 1994 .

A study of estimation of balance degree using CMRR mesurement for power distribution interconnection on printed circuit board

Hideki Asai, Mutsumi Shimazaki, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

An application of Verilog-A to modeling of back propagation algorithm in neural networks

Hideki Asai, A. Kamo, Takayuki Watanabe, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

A comparison between latency insertion method and relaxation method in transient thermal analysis

Tadatoshi Sekine, Hideki Asai, Anh Ha Ngo, 2016, 2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC).

Accelerating the large-scale simulation of power distribution networks by using the multi-GPU LIM

Hideki Asai, Yuta Inoue, 2014, 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC).

Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method

Hideki Asai, Takayuki Watanabe, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A new piecewise-linear simulation algorithm using switch-level pattern dynamics

Hideki Asai, S. Suzuki, S. Suzuki, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Mixed mode circuit simulator SPLIT2 using dynamic network separation and latency

Masakatsu Nishigaki, Hideki Asai, Nobuyuki Tanaka, 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

A Robust Quasi-Newton Training with Adaptive Momentum for Microwave Circuit Models in Neural Networks

Hideki Asai, Hiroshi Ninomiya, Shahrzad Mahboubi, 2020 .

Network analysis by hierarchical tearing method

Hideki Asai, Shinsaku Mori, 1985, Systems and Computers in Japan.

Transient simulation of coupled lossy interconnects by window partitioning technique

Hideki Asai, Vijaya Gopal Bandi, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

HIDE : Hierarchical Decomposition System for Preprocessing of Circuit Simulation

Masakatsu Nishigaki, Hideki Asai, Nobuyuki Tanaka, 1990 .

Locally implicit block leapfrog scheme for PDN simulation

Hideki Asai, 2013, 2013 International Conference on Electromagnetics in Advanced Applications (ICEAA).

Adaptive Least-Squares Method for MIMO System Identification

Hideki Asai, Yuichi Tanji, Takayuki Watanabe, 2002 .

Under relaxation techniques for stable convergence in nonlinear circuit simulation

Hideki Asai, T. Kokado, 1989, IEEE International Symposium on Circuits and Systems,.

Generalized method of the time-domain circuit simulation based on LIM with MNA formulation

Hideki Asai, Yuichi Tanji, Hidemasa Kubota, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Neural Network Simulator for Spatiotemporal Pattern Analysis Based on ASSIST2

Hideki Asai, A. Kamo, Teru Yoneyama, 1997 .

Iterated timing analysis with dynamic partitioning technique for bipolar transistor circuits

Masakatsu Nishigaki, Hideki Asai, Koichi Hayashi, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Design and Simulation of Neural Network Digital Sequential Circuits (Special Section of Papers Selected from JTC-CSCC'93)

Hideki Asai, Hiroshi Ninomiya, 1994 .

A design method of DWT analog neuro chip for VLSI implementation

Hideki Asai, Hiroshi Ninomiya, H. Adachi, 1997, IEEE Instrumentation and Measurement Technology Conference Sensing, Processing, Networking. IMTC Proceedings.

Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling

Akio Ushida, Yoshifumi Nishio, Hideki Asai, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

高速三次元電磁界・回路シミュレーション技術の現状と将来展望;高速三次元電磁界・回路シミュレーション技術の現状と将来展望;Current Status and Future Trend of Fast 3D Electromagnetic/Circuit Simulation Technology

Tadatoshi Sekine, Hideki Asai, Yuta Inoue, 2014 .

Relaxation-Based Transient Analysis of Lossy Coupled Transmission Lines Circuits Using Delay Evaluation Technique

Hideki Asai, A. Kamo, Takayuki Watanabe, 1997 .

Design and Simulation of Neural Network Digital Sequential Circuits

Hideki Asai, Hiroshi Ninomiya, 1993 .

Application of ADE-LIM to multiconductor transmission lines with nonlinear drivers and terminations

Tadatoshi Sekine, Hideki Asai, Hiroki Kurobe, 2010, 2010 IEEE Electrical Design of Advanced Package & Systems Symposium.

Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation

Hideki Asai, Yuya Nakazono, H. Asai, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Interconnect simulation using FDTD method with variable mesh size technique

Hirofumi Suzuki, Hideki Asai, Hidemasa Kubota, 2005, Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005..

Signal propogation in 3D interconnect

Hideki Asai, Joungho Kim, 2014 .

A study of Hopfield neural networks with external noises

Hideki Asai, T. Kamio, Hiroshi Ninomiya, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

Two floating resistor circuits and their applications to synaptic weights in analog neural networks

Hideki Asai, Teru Yoneyama, Shashidhar Tantry, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Sparsely Interconnected Neural Networks for Associative Memory Using 2-Dimensional Discrete Walsh Transform

Hideki Asai, Takeshi Kamio, 1998 .

Stabilized Mixed Finite-Element Time-Domain Method for Fast Transient Analysis of Multiscale Electromagnetic Problems

Tadatoshi Sekine, Hideki Asai, Yohei Oikawa, 2018, IEEE Transactions on Microwave Theory and Techniques.

A Nesterov's Accelerated quasi-Newton method for Global Routing using Deep Reinforcement Learning pdf

Hideki Asai, Takeshi Kamio, S. Indrapriyadarsini, 2020, ArXiv.

Equivalent Properties between Latency Insertion Method (LIM) and Semi-Implicit Numerical Integration Method

Tadatoshi Sekine, Hideki Asai, Tomoki Ishimaru, 2009 .

Efficient Simulation of Lossy Coupled Transmission Lines by the Application of Window Partitioning Technique to the Waveform Relaxation Approach (Special Section on Nonlinear Theory and Its Applications)

Hideki Asai, Vijaya Gopal Bandi, 1994 .

A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition

Hideki Asai, Masaki Unno, Shuichi Aono, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Convergence of Hopfield neural network for orthogonal transformation

Hideki Asai, Takeshi Kamio, Hiroshi Ninomiya, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Discrete Walsh Transform by Linear Programming Neural Net

Hideki Asai, Takeshi Kamio, Hiroshi Ninomiya, 1994 .

Mixed-Signal Simulation by Dynamic Circuit Partitioning

Masakatsu Nishigaki, Hideki Asai, Hisashi Irii, 1996 .

Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane

Tadatoshi Sekine, Hideki Asai, Yuichi Tanji, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A locally implicit leapforg scheme for fast simulation of triangle-meshed PDN with nonlinear circuit

Hideki Asai, Shingo Okada, 2014, 2014 International Symposium on Electromagnetic Compatibility.

Special Section on nonlinear circuits and systems and their applications

Hideki Asai, 2017 .

An approach for practical use of common-mode noise reduction technique for in-vehicle electronic equipment

Hideki Asai, Yuji Okazaki, Takanori Uno, 2010, EMC 2010.

Applications of frequency-dependent transmission-line model to INDUCTWISE and fast transient analysis (Special section on papers awarded the student paper award at NCSP'07)

Hideki Asai, Takayuki Watanabe, Tadashi Ishikawa, 2007 .

An approach for practical use of common-mode noise reduction technique for in-vehicle electronic equipment

Atsushi Nakamura, Hideki Asai, Kouji Ichikawa, 2010, 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility.

Efficient Techniques of Macromodel Synthesis for Interconnects and Electromagnetic Emissions Using FDTD Method

Hideki Asai, A. Kamo, Takayuki Watanabe, 2001 .

Quasi-one-step Gauss-Jacobi method for large-scale interconnect analysis via RLCG-MNA formulation

Hideki Asai, Yuichi Tanji, Hidemasa Kubota, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Implicit steepest descent method and its analogy with charge-up method based on virtual capacitors in network analysis

Hideki Asai, 1988, 1988., IEEE International Symposium on Circuits and Systems.

Fast Transient Analysis of Nonuniform Multiconductor Transmission Lines Using HIE-Block-LIM

Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai, 2013, IEEE Microwave and Wireless Components Letters.

An optimization system with parallel processing for reducing electromagnetic interference on electronic control unit

Hideki Asai, Takanori Uno, Yuji Okazaki, 2009, 2009 11th Electronics Packaging Technology Conference.

Expanded GMC for transient analysis of transmission line networks

Hideki Asai, Takayuki Watanabe, Atsushi Kamo, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

An Efficient Simulation Method of Linear/Nonlinear Mixed Circuits Based on Hybrid Model Order Reduction Technique

Hideki Asai, A. Kamo, Takayuki Watanabe, 2004 .

Subgrid-based equivalent circuit for transient thermal analysis using latency insertion method

Tadatoshi Sekine, Hideki Asai, Anh Ha Ngo, 2017, 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI).

Triangular Subcell Method for Efficient Equivalent Circuit Modeling of Power Delivery Network

Tadatoshi Sekine, Hideki Asai, Ikki Arakaki, 2015 .

Efficient modeling and analysis of multilayered power distribution network by using conformal mesh and block-type leapfrog scheme

Tadatoshi Sekine, Hideki Asai, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method

Hideki Asai, Takeshi Kamio, S. Indrapriyadarsini, 2020, ISCAS.

Efficient electromagnetic simulation of PCB with SPICE elements by using HIE-FDTD method

Hideki Asai, Yuta Inoue, 2018, 2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC).

Multi-Rate Locally Implicit Block Leapfrog Scheme for Fast Transient Analysis of Multi-Layered Power/Ground Planes

Tadatoshi Sekine, Hideki Asai, Shingo Okada, 2016, IEEE Microwave and Wireless Components Letters.

Design optimization of automotive electronic control unit using the analysis of common-mode current by fast electromagnetic field solver

Hideki Asai, Masaki Unno, Takanori Uno, 2010, The 40th European Microwave Conference.

An EMI Simulator Based on the Parallel-Distributed FDTD Method for Large-Scale Printed Wiring Boards

Kenji Araki, Hideki Asai, Takayuki Watanabe, 2002, Proceedings: 6th IEEE Workshop on Signal Propagation on Interconnects.

BP-based learning system with analog neuro-LSI

Hideki Asai, M. Yoshida, T. Yoneyama, 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).

Circuit and Electromagnetic Hybrid Simulation Technique Based on Waveform Relaxation Method

Hideki Asai, Masaki Unno, 2009 .

A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation

Hideki Asai, Shinsuke Manabe, 2004, Neural Processing Letters.

Evaluation method of balance mismatch using CMRR measurement for printed circuit board

Hideki Asai, Mutsumi Shimazaki, 2014, 2014 International Symposium on Electromagnetic Compatibility, Tokyo.

ThreeDimensional Module Packing bySimulated Annealing

Hideki Asai, Hiroshi Ninomiya, Hirokazu Yamagishi, 2005 .

GPGPU-based ADE-FDTD method for fast electromagnetic field simulation and its estimation

Hideki Asai, Masaki Unno, Shuichi Aono, 2011, Asia-Pacific Microwave Conference 2011.

Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits

Tadatoshi Sekine, Hideki Asai, Hiroki Kurobe, 2012, 17th Asia and South Pacific Design Automation Conference.

A low voltage floating resistor having positive and negative resistance values

Hideki Asai, Teru Yoneyama, Shashidhar Tantry, 2002, Asia-Pacific Conference on Circuits and Systems.

Fast network simulation using domain decomposition with model-order reduction (Special section on papers awarded the student paper award at NCSP'07)

Hideki Asai, Toshio Unno, 2007 .

High-speed electromagnetic field simulation by HIE-FDTD method with GPGPU

Hideki Asai, Masaki Unno, 2010, 2010 IEEE Electrical Design of Advanced Package & Systems Symposium.

Conformal equivalent circuit model and leapfrog alternating direction implicit formulation for fast simulation of power delivery network

Tadatoshi Sekine, Hideki Asai, 2015, 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC).

Special parallel processor for lu decomposition of a large-scale sparse matrix

Mamoru Tanaka, Hideki Asai, Mitsuo Asai, 1987, Systems and Computers in Japan.

Relaxation-based steady-state analysis of single- and multi-conductor transmission lines in frequency domain

Hideki Asai, Takeshi Senoo, Hiroaki Makino, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network

Tadatoshi Sekine, Hideki Asai, 2013, ECTC 2013.

Design method of neural networks for limit cycle generator

Hideki Asai, Teru Yoneyama, Hiroshi Ninomiya, 1999, IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339).

Relaxation-Based Shooting Method for Steady-state Analysis of FET Circuits

Hideki Asai, Takeshi Yonehara, 1994 .

Acceleration of large electromagnetic simulation including non-orthogonally aligned thin structures by using multi-GPU HIE/C-FDTD method

Hideki Asai, Yuta Inoue, 2015, 2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

A comparison of equivalent circuit models of power/ground planes based on Delaunay triangulation in transient analysis

Hideki Asai, Takayuki Watanabe, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

An Adaptive Stochastic Nesterov Accelerated Quasi Newton Method for Training RNNs pdf

Hideki Asai, S. Indrapriyadarsini, Hiroshi Ninomiya, 2019, ArXiv.

SI/PI/EMI simulation techniques and application to automotive electronic design issues

Hideki Asai, H. Asai, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

Two-Stage Tabu Search for Nonslicing Floorplan Problem Represented by O-Tree (Special Issue on Nonlinear Circuits and Signal Processing)

Hideki Asai, Hiroshi Ninomiya, Kimihiko Numayama, 2007 .

Generating stable and sparse reluctance/inductance matrix under insufficient conditions

Hideki Asai, Yuichi Tanji, Takayuki Watanabe, 2008, 2008 Asia and South Pacific Design Automation Conference.

Architecture for simulation system with consideration of circuit partition

Hideki Asai, Nobuyuki Tanaka, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

Neuro-Based Optimization Algorithm for Three Dimensional Puzzles

Hideki Asai, Hiroyuki Yamamoto, Hiroshi Ninomiya, 1996 .

Momentum Acceleration of Quasi-Newton Training for Neural Networks

Hideki Asai, S. Indrapriyadarsini, Hiroshi Ninomiya, 2019, PRICAI.

A Neuro-Based Optimization Algorithm for Rectangular Puzzles(Special Section of Papers Selected from ITC-CSCC'97)

Hideki Asai, Hiroshi Ninomiya, Hiroyuki Yamamoto, 1998 .

Numerical Stability and Multirate Effect in Waveform Relaxation Algorithm with Under Relaxation Technique

Hideki Asai, Koichi Hayashi, 1991 .

Fast simulation of multilayered power delivery network using multilayered triangular subcell method and block-type leapfrog scheme

Tadatoshi Sekine, Hideki Asai, Ikki Arakaki, 2016, 2016 URSI Asia-Pacific Radio Science Conference (URSI AP-RASC).

Three dimensional module packing by simulated annealing

Hideki Asai, Hiroshi Ninomiya, Hirokazu Yamagishi, 2005, 2005 IEEE Congress on Evolutionary Computation.

A framework for fast SI/PI simulation with acceleration techniques

Tadatoshi Sekine, Hideki Asai, Yuta Inoue, 2017, 2017 International Conference on Electromagnetics in Advanced Applications (ICEAA).

Fast transient analysis of 3-D stacked on-chip power distribution network with power/ground through silicon vias by using block latency insertion method

Tadatoshi Sekine, Hideki Asai, Daisei Nagata, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

Fast simulation of power distribution networks based on semi-implicit numerical integration method and RLCG-MNA formulation

Tadatoshi Sekine, Hideki Asai, Tomoki Ishimaru, 2009, 2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS).

Mixed Mode Circuit Simulation Using Dynamic Partitioning (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)

Masakatsu Nishigaki, Hideki Asai, Nobuyuki Tanaka, 1993 .

Present Status and Future Trend of Large-Scale/High-Speed/High-Precision Simulation Technology

Hideki Asai, Yuta Inoue, Shingo Okada, 2016 .

Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects

Hideki Asai, Yuichi Tanji, 2004, Proceedings. 41st Design Automation Conference, 2004..

Behavioral modeling of EM devices by selective orthogonal matrix least-squares method

Hideki Asai, Yuichi Tanji, Takayuki Watanabe, 2003, ASP-DAC '03.

Fast timing analysis of plane circuits via two-layer CNN-based modeling

Akio Ushida, Yoshifumi Nishio, Hideki Asai, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Analyses of Large Scale PWB with Parallel-Distributed 3-Dimension Electromagnetic Simulator“BLESS”

Hideki Asai, Takayuki Watanabe, Kenji Araki, 2006 .

GPU-based acceleration of the time-domain electrical full-wave solvers in PI/SI/EMI simulation

Hideki Asai, 2011, 2011 International Conference on Electromagnetics in Advanced Applications.

Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via

Tadatoshi Sekine, Hideki Asai, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Efficient circuit/electromagnetic hybrid simulation for the electrostatic discharge events

Tsuyoshi Takada, Tadatoshi Sekine, Hideki Asai, 2013 .

Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters

Hideki Asai, Yuichi Tanji, Hidemasa Kubota, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values

Hideki Asai, Teru Yoneyama, Shashidhar Tantry, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Frequency Domain Analysis of Transmission Lines by Harmonic Balance and Characteristic Model

Hideki Asai, Hiroaki Makino, Takeshi Senoo, 1993 .

Fast transient simulation of multilayered power delivery network by using the stabilized explicit method

Tadatoshi Sekine, Hideki Asai, 2015, 2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity.

Parallel-distributed block-LIM-based fast transient simulation of tightly coupled transmission lines

Tadatoshi Sekine, Hideki Asai, Yuta Inoue, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

Nonlinear locally implicit LIM for the simulation of PDN modeled by triangular meshes

Tadatoshi Sekine, Hideki Asai, Shingo Okada, 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

Block-Latency Insertion Method (Block-LIM) for Fast Transient Simulation of Tightly Coupled Transmission Lines

Tadatoshi Sekine, Hideki Asai, 2011 .

A new CMOS 4Q–multiplier using linear and saturation regions complementally

Hideki Asai, Teru Yoneyama, T. Suzuki, 2002 .

Fast Circuit Simulation Based on Parallel-Distributed LIM using Cloud Computing System

Tadatoshi Sekine, Hideki Asai, Yuta Inoue, 2010 .

GPGPU-based Latency Insertion Method: Application to PDN simulations

Tadatoshi Sekine, Hideki Asai, Yuta Inoue, 2009, 2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS).

Fast Simulation of Multiconductor Transmission Lines Using Nodal Block Relaxation (NBR) Method

Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai, 2012 .

Design method of limit cycle generator by hysteresis neural networks

Hideki Asai, Teru Yoneyama, Hiroshi Ninomiya, 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium.

Availability of Gate Level Node Tearing in Bipolar Circuit Simulation by Direct Method

Hideki Asai, 1988 .

Time Domain Circuit Simulation Using Nonlinear Reduction Technique

Hideki Asai, A. Kamo, Takayuki Watanabe, 2003 .

Momentum acceleration of quasi-Newton based optimization technique for neural network training

Hideki Asai, Hiroshi Ninomiya, Shahrzad Mahboubi, 2021, Nonlinear Theory and Its Applications, IEICE.

A modified limited memory Nesterov's accelerated quasi-Newton pdf

Hideki Asai, Takeshi Kamio, S. Indrapriyadarsini, 2021, ArXiv.

Frequency domain latency and relaxation-based harmonic analysis of nonlinear circuits

Hideki Asai, H. Asai, H. Makino, 1991, [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems.

A Fast Algorithm for Spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic (Special Section on Nonlinear Theory and Its Applications)

Hideki Asai, A. Kamo, Teru Yoneyama, 1998 .

Electrostatic field simulations of curved conductors by using method of moments based on isogeometric analysis

Tadatoshi Sekine, Hideki Asai, Kenjiro T. Miura, 2014, 2014 International Symposium on Electromagnetic Compatibility.

Neural Networks for Digital Sequential Circuits

Hideki Asai, Hiroshi Ninomiya, 1994 .

A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values

Hideki Asai, Teru Yoneyama, Shashidhar Tantry, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain

Hideki Asai, A. Kamo, Kenichi Suzuki, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Positive Negative Resistor for Synaptic Weights

Hideki Asai, Teru Yoneyama, Shashidhar Tantry, 2002 .

Relaxation-based simulation of nonlinear circuits in the frequency domain

Hideki Asai, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

Locally stabilized explicit method for fast transient analysis of inhomogeneously-meshed plane structures

Tadatoshi Sekine, Hideki Asai, 2014, 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC).

Incomplete Shooting Method for Finding Steady State Responses of Nonlinear Circuits

Hiroo Sekiya, Hideki Asai, Yuichi Tanji, 2005 .

Advanced PI / SI / EMI Simulation Technology for High-Speed Electronic Design-Toward chip / package / board co-design-Hideki Asai Shizuoka

Hideki Asai, 2010 .

Evaluation Method of Common-mode Control Using the CMRR in Power Distribution Interconnection on Printed Circuit Board

Hideki Asai, Mutsumi Shimazaki, Shinya Nishi, 2013 .

Alternating-direction explicit FDTD method for three-dimensional full-wave simulation

Hideki Asai, Masaki Unno, Shuichi Aono, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

Analog neuro‐based approach to tiling problem using fitting function of polyominoes

Hideki Asai, Hiroshi Ninomiya, Takeshi Nakayama, 2000 .

A Hybrid Implicit–Explicit and Conformal (HIE/C) FDTD Method for Efficient Electromagnetic Simulation of Nonorthogonally Aligned Thin Structures

Tadatoshi Sekine, Hideki Asai, Hideaki Muraoka, 2015, IEEE Transactions on Electromagnetic Compatibility.

Relaxation-Based Circuit Simulation Techniques in the Frequency Domain

Hideki Asai, Hiroaki Makino, 1993 .

A Neuro-Based Optimization Algorithm for Three Dimensional Cylindric Puzzles (Special Section of Papers Selected from ITC-CSCC'96)

Hideki Asai, Hiroshi Ninomiya, Takeshi Nakayama, 1997 .