Poul Frederick Williams

Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking

Armin Biere, Edmund M. Clarke, Anubhav Gupta, 2000, CAV.

Formal Verification based on Boolean Expression Diagrams

Poul Frederick Williams, P. F. Williams, 2001, Electronic Notes in Theoretical Computer Science.

Satisfiability checking using Boolean Expression Diagrams

Henrik Reif Andersen, Henrik Hulgaard, Poul Frederick Williams, 2002, International Journal on Software Tools for Technology Transfer.

Combinational Logic-Level Verification using Boolean Expression Diagrams

Henrik Reif Andersen, Henrik Hulgaard, Poul Frederick Williams, 1997 .

Equivalence checking of hierarchical combinational circuits

Poul Frederick Williams, H. Hulgaard, H. Andersen, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Equivalence checking of combinational circuits using Boolean expression diagrams

Henrik Reif Andersen, Henrik Hulgaard, Poul Frederick Williams, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Bypassing BDD construction for reliability analysis

Antoine Rauzy, Poul Frederick Williams, Macha Nikolskaïa, 2000, Inf. Process. Lett..

Satisfiability Checking Using Boolean Expression Diagrams

Henrik Reif Andersen, Henrik Hulgaard, Poul Frederick Williams, 2001, TACAS.

Formal Verification based on Boolean Expression Diagrams

Poul Frederick Williams, P. F. Williams, 2001, Electronical Notes in Theoretical Computer Science.