S. Demuynck

发表

Intrinsic reliability of local interconnects for N7 and beyond

Ivan Ciofi, Chen Wu, W. Gao, 2015, 2015 IEEE International Reliability Physics Symposium.

Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics

M. Van Hove, T. Chiarella, I. Debusschere, 2006, 2006 IEEE International Conference on Microelectronic Test Structures.

Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond

P. Weckx, S. Demuynck, A. Soussou, 2019, Advanced Lithography.

Evaluation of integration schemes for contact-hole grapho-epitaxy DSA: a study of substrate and template affinity control

T. Yamauchi, S. Demuynck, K. Nafus, 2014, Advanced Lithography.

Enabling CMOS Scaling Towards 3nm and Beyond

J. Ryckaert, P. Weckx, A. Mocuta, 2018, 2018 IEEE Symposium on VLSI Technology.

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Diederik Verkest, Anabela Veloso, Aaron Thean, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Towards high performance sub-10nm finW bulk FinFET technology

Naoto Horiguchi, Jérôme Mitard, P. Eyben, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

The Complementary FET (CFET) for CMOS scaling beyond N3

G. Bouche, J. Ryckaert, D. Mocuta, 2018, 2018 IEEE Symposium on VLSI Technology.

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

J. Ryckaert, T. Chiarella, N. Horiguchi, 2020, 2020 IEEE Symposium on VLSI Technology.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Role of Defects in the Reliability of HfO2/Si-Based Spacer Dielectric Stacks for Local Interconnects

K. Croes, S. Demuynck, C. Wu, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects

N. Horiguchi, K. Croes, S. Demuynck, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Imaging performance of the EUV alpha semo tool at IMEC

K. Ronse, S. Demuynck, D. Goossens, 2008, SPIE Advanced Lithography.

Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation

D. Mocuta, R. Ritzenthaler, N. Horiguchi, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination

M. Van Hove, S. Demuynck, K. Maex, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

Contact module at dense gate pitch technology challenges

K. Croes, S. Demuynck, T. Kauerauf, 2014, IEEE International Interconnect Technology Conference.

Impact of Cu contacts on front-end performance: a projection towards 22nm node

M. Van Hove, T. Chiarella, G. Van den bosch, 2006, 2006 International Interconnect Technology Conference.

Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Wen-Chin Lee, S. Demuynck, Jianxin Lei, 2008, IEEE Transactions on Electron Devices.

Impact of the barrier/dielectric interface quality on reliability of Cu porous-low-k interconnects

S. Demuynck, P. Roussel, K. Maex, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Cu Wire resistance improvement using Mn-based Self-Formed Barriers

K. Croes, S. Demuynck, I. Ciofi, 2014, IEEE International Interconnect Technology Conference.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Quantifying LER to predict its impact on BEOL TDDB reliability at 20nm ½ pitch

S. Demuynck, M. Stucchi, D. De Roest, 2010, 2010 IEEE International Interconnect Technology Conference.

Initial void chacterization in 30nm wide polycrystalline Cu line using a local sense EM test structure

K. Croes, M. Lofrano, S. Demuynck, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

D. Mocuta, R. Ritzenthaler, W. Vandervorst, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

A. Mercha, D. Verkest, M. Badaroglu, 2012, International Electron Devices Meeting.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Cobalt bottom-up contact and via prefill enabling advanced logic and DRAM technologies

K. Croes, S. Demuynck, Marleen H. van der Veen, 2015, 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).