W. Reczek

Latch-up Free CMOS Using Buried Polysilicon Diodes

W. Reczek, J. Winnerl, F. Bonner, 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

Cost reduction using systematic target setting of the reference fab methodology

Hans Ehm, W. Reczek, R. Plieninger, 2001, 2001 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (IEEE Cat. No.01CH37160).

New Concepts for Wordline Driving Circuits in CMOS Dynamic Random Access Memories

J. Harter, W. Reczek, R. Strunz, 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.

CMOS output buffers for megabit DRAMs

J. Harter, W. Reczek, Wolfgang Pribyl, 1988 .

Guidelines For Latch-up Characterization Techniques

W. Reczek, W. Pribyl, 1988, Proceedings of the IEEE International Conference on Microelectronic Test Structures.

Latch-Up Free VLSI CMOS Circuits Considering Power-On Transients

W. Reczek, J. Winnerl, W. Pribyl, 1988, ESSDERC '88: 18th European Solid State Device Research Conference.

Noise Considerations on High Density DRAMs: Problems and Solutions

J. Harter, W. Reczek, F. Bonner, 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference.

Design Concept for Radiation Hardening of Low Power and Low Voltage Dynamic Memories

W. Reczek, K. Hoffmann, H. Schleifer, 1994, ESSCIRC '94: Twientieth European Solid-State Circuits Conference.

Improvement of latchup hardness by geometry and technology tuning

C. Mazure, D. Takacs, W. Reczek, 1988 .

Static and transient latch-up hardness in N-well CMOS with on-chip substrate bias generator

D. Takacs, W. Reczek, J. Winnerl, 1985, 1985 International Electron Devices Meeting.