Marcus Bednara

发表

Tradeoff analysis and architecture design of a hybrid hardware/software sorter

Jürgen Teich, Marcus Bednara, Oliver Beyer, 2000, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors.

FPGA designs of parallel high performance GF(2233) multipliers

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2003, ISCAS.

A new approach for on-line placement on reconfigurable devices

Jürgen Teich, Ali Ahmadinia, Marcus Bednara, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach

Umut Durak, Jürgen Becker, George Theodoridis, 2018, ARC.

Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms

Jürgen Teich, Marcus Bednara, 2004, The Journal of Supercomputing.

A high performance VLIW processor for finite field arithmetic

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Reconfigurable implementation of elliptic curve crypto algorithms

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

Generation of Distributed Loop Control

Jürgen Teich, Marcus Bednara, Frank Hannig, 2002, Embedded Processor Design Challenges.

Real time polarization sensor image processing on an embedded FPGA/multi-core DSP system

Marcus Bednara, Katarzyna Chuchacz-Kowalczyk, M. Bednara, 2015, Europe Optics + Optoelectronics.

Automated Design Space Exploration on System Level for Embedded Systems

Achim Rettberg, Wolfram Hardt, Marcus Bednara, 2000 .

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach

Umut Durak, Harald Bucher, Jürgen Becker, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware

Jürgen Teich, Marcus Bednara, Frank Slomka, 2003, EURASIP J. Adv. Signal Process..

Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration

Jürgen Teich, Ali Ahmadinia, Marcus Bednara, 2004, IEEE International Parallel and Distributed Processing Symposium.

Interactive Parallelization of Embedded Real-Time Applications Starting from Open-Source Scilab & Xcos

Umut Durak, Marcus Bednara, Michael Schöberl, 2018 .

Tradeoff analysis of FPGA based elliptic curve cryptography

Jürgen Teich, Marcus Bednara, Joachim von zur Gathen, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).