Shen-Tien Lin

Fail pattern identification for memory built-in self-repair

Cheng-Wen Wu, Chin-Lung Su, Kun-Lun Luo, 2004, 13th Asian Test Symposium.

Accelerating dynamic peak power analysis using an essential-signal-based methodology

Chia-Chih Yen, Hermes Lin, Jing-Yang Jou, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

A testable BIST design for PLL

Kun-Lun Luo, Yeong-Jar Chang, Shen-Tien Lin, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Embedded memory diagnostic data compression using differential address

Cheng-Wen Wu, Chin-Lung Su, Rei-Fu Huang, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Software-enabled design visibility enhancement for failure analysis process improvement

Chia-Chih Yen, Etienne Auvray, Shen-Tien Lin, 2009, 2009 International Symposium on VLSI Design, Automation and Test.