Chung-Yang Huang

发表

QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure

Chih-Chun Lee, Chi-An Wu, Ting-Hao Lin, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Conquering the scheduling alternative explosion problem of SystemC symbolic simulation

Chun-Nan Chou, Chung-Yang Huang, Chen-Kai Chu, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques

Kwang-Ting Cheng, Chung-Yang Huang, 2000, DAC.

Speeding up SoC virtual platform simulation by data-dependency aware virtual synchronization

Chung-Yang Huang, Kuen-Huei Lin, Siao-Jie Cai, 2008, 2008 International SoC Design Conference.

Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation

Kuan-Lun Tseng, Winston H. Hsu, Yen-Liang Lin, 2017, 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR).

Scalable exploration of functional dependency by interpolation and incremental SAT solving

Jie-Hong Roland Jiang, Alan Mishchenko, Chih-Chun Lee, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization

Shao-Lun Huang, Chang-Hong Hsu, Kai-Fu Tang, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Automatic abstraction refinement of TR for PDR

Chung-Yang Huang, Ming-Jen Yang, Kuan Fan, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction

Chun-Nan Chou, Po-Kai Huang, Kai-Fu Tang, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification

Chung-Yang Huang, Hu-Hsi Yeh, Cheng-Yin Wu, 2012, TACAS.

A unified Multi-Corner Multi-Mode static timing analysis engine

Chung-Yang Huang, Jing-Jia Nian, Shihgeng Tsai, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

SoC HW/SW verification and validation

Chung-Yang Huang, Chih-Jen Hsu, Yu-Fan Yin, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Formal deadlock checking on high-level SystemC designs

Chun-Nan Chou, Chang-Hong Hsu, Chung-Yang Huang, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques

Chun-Ju Yang, Bo-Han Wu, Chung-Yang Huang, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

An analysis of ATPG and SAT algorithms for formal verification

Kwang-Ting Cheng, Ganapathy Parthasarathy, Chung-Yang Huang, 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.

Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling

Chung-Yang Huang, Kuen-Huei Lin, Siao-Jie Cai, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

To SAT or Not to SAT: Scalable Exploration of Functional Dependency

Jie-Hong Roland Jiang, Alan Mishchenko, Chih-Chun Lee, 2010, IEEE Transactions on Computers.

Using SAT-based craig interpolation to enlarge clock gating functions

Ting-Hao Lin, Chung-Yang Huang, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Adaptive interpolation-based model checking

Chung-Yang Huang, Cheng-Yin Wu, Chien-Yu Lai, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Automatic Constraint Generation for guided random simulation

Chung-Yang Huang, Hu-Hsi Yeh, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

LIBRA—a library-independent framework for post-layout performance optimization

Yucheng Wang, Kwang-Ting Cheng, Chung-Yang Huang, 1998, ISPD '98.

A false-path aware Formal Static Timing Analyzer considering simultaneous input transitions

Chung-Yang Huang, Shihheng Tsai, 2009, 2009 46th ACM/IEEE Design Automation Conference.

QuteVP: A multi-million-instructions-per-second virtual platform for SoC hardware/software co-design

Chung-Yang Huang, Kuen-Huei Lin, Yuan-Lung Li, 2009, 2009 International Conference on Communications, Circuits and Systems.

A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification

Chun-Ju Yang, Bo-Han Wu, Chung-Yang Huang, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

AQUILA: An Equivalence Checking System for Large Sequential Designs

Shi-Yu Huang, Kwang-Ting Cheng, Forrest Brewer, 2000, IEEE Trans. Computers.

An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation

Chung-Yang Huang, Hsin-Cheng Lin, Yu-Fu Yeh, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

QuteSAT: a robust circuit-based SAT solver for complex circuit structure

Chih-Chun Lee, Chi-An Wu, Ting-Hao Lin, 2007 .

A robust functional ECO engine by SAT proof minimization and interpolation techniques

Jie-Hong Roland Jiang, Chun-Ju Yang, Bo-Han Wu, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach

Shu-Yen Lin, Chung-Yang Huang, Yu-Fu Yeh, 2016 .

A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking

Chi-An Wu, Chung-Yang Huang, Cheng-Yin Wu, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints

Chung-Yang Huang, Shihheng Tsai, Man-Yu Li, 2012, 17th Asia and South Pacific Design Automation Conference.

A robust general constrained random pattern generator for constraints with variable ordering

Bo-Han Wu, Chung-Yang Huang, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Interpolation-based incremental ECO synthesis for multi-error logic rectification

Po-Kai Huang, Kai-Fu Tang, Chi-An Wu, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Interpolant generation without constructing resolution graph

Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method

Chi-An Wu, Chung-Yang Huang, Hsin-Cheng Lin, 2011, 2011 Design, Automation & Test in Europe.

Symbolic model checking on SystemC designs

Chun-Nan Chou, Chiao Hsieh, Chung-Yang Huang, 2012, DAC Design Automation Conference 2012.

Property-specific sequential invariant extraction for SAT-based unbounded model checking

Chung-Yang Huang, Hu-Hsi Yeh, Cheng-Yin Wu, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Improving Constant-Coefficient Multiplier Verification by Partial Product Identification

Kei-Yong Khoo, Chung-Yang Huang, Chao-Yue Lai, 2008, 2008 Design, Automation and Test in Europe.

A robust constraint solving framework for multiple constraint sets in Constrained Random Verification

Bo-Han Wu, Chung-Yang Huang, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking

Kwang-Ting Cheng, Chung-Yang Huang, K. Cheng, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Static property checking using ATPG vs. BDD techniques

Kwang-Ting Cheng, Huan-Chih Tsai, Bwolen Yang, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

QuteIP: An IP qualification framework for System on Chip

Ting-Hao Lin, Chung-Yang Huang, Hsing-Chih Hung, 2007, SoCC.