Jun Han

发表

SoundUAV: Towards Delivery Drone Authentication via Acoustic Noise Fingerprinting

Soundarya Ramesh, Thomas Pathier, Jun Han, 2019 .

Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm

Ying Zhang, Yalong Pang, Xiaoyang Zeng, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

An Energy-Proportion Synchronization Method for IR-UWB Communications

Jing Wang, Xiaoyang Zeng, Lang Mai, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Instruction set extension and hardware acceleration for SVM application toward a vector processor

Yalong Pang, Xiaoyang Zeng, Yujie Huang, 2017, 2017 International SoC Design Conference (ISOCC).

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

Yuli Zhang, Xiaoyang Zeng, Jun Han, 2012, IEICE Trans. Electron..

Cryptographie coprocessor design for IoT sensor nodes

Shan Huang, Xiaoyang Zeng, Zhicheng Xie, 2016, 2016 International SoC Design Conference (ISOCC).

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design

Zhiyi Yu, Xiaoyang Zeng, Jianwei Yang, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation

Xiaoyang Zeng, Jia Zhao, Jun Han, 2007, 2007 IEEE Workshop on Signal Processing Systems.

A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT

Xiaoyang Zeng, Yao Zou, Gaowei Xu, 2015, IEEE Signal Processing Letters.

A new method for recognising radar radiating-source

Yan Mao, Jun Han, Ming-Hao He, 2007, 2007 International Conference on Wavelet Analysis and Pattern Recognition.

An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor

Shan Huang, Xiaoyang Zeng, Yicheng Zhang, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS

Zhiyi Yu, Zhang Zhang, Yibo Fan, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A SIMD multiplier-accumulator design for pairing cryptography

Xiaoyang Zeng, Weizhen Wang, Jun Han, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A control scheme for a 65nm 32×32b 4-read 2-write register file

Zhiyi Yu, Xiaoyang Zeng, Xingxing Zhang, 2011, 2011 9th IEEE International Conference on ASIC.

Radar emitter signals classification using kernel principle component analysis and fuzzy support vector machines

Yan Mao, Jun Han, Ming-Qiu Ren, 2007, 2007 International Conference on Wavelet Analysis and Pattern Recognition.

A security processor based on MIPS 4KE architecture

Yang Li, Shuai Wang, Xiaoyang Zeng, 2011, 2011 9th IEEE International Conference on ASIC.

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process

Yi Li, Xu Cheng, Zhiyi Yu, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost

Xin Li, Shan Huang, Xiaoyang Zeng, 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

An ultra low-power and area-efficient baseband processor for WBAN transmitter

Xiaoyang Zeng, Yao Zou, Jun Han, 2013, 2013 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference.

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform

Zhiyi Yu, Shuai Wang, Wei Huang, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A low-cost SoC implementation of AES algorithm for bio-signals

Lijun Zhou, Jianwei Yang, Xiaoyang Zeng, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Optimized digital automatic gain control for DVB-S2 system

Chuan Wu, Xiaoyang Zeng, Jun Han, 2010, 2010 Wireless Telecommunications Symposium (WTS).

MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device

Xin Li, Xiaoyang Zeng, Bingyi Zhang, 2018, 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP).

A NoC-based multi-core architecture for IEEE 802.11i CCMP

Yang Li, Shuai Wang, Xiaoyang Zeng, 2011, 2011 9th IEEE International Conference on ASIC.

FPGA-based efficient implementation of SURF algorithm

Ying Zhang, Yujie Huang, Xiaoyang Zeng, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Low power design for FIR filter

Xiaoyang Zeng, Yao Zou, Gaowei Xu, 2013, 2013 IEEE 10th International Conference on ASIC.

A configurable nonlinear operation unit for neural network accelerator

Xin Li, Yujie Cai, Xiaoyang Zeng, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals

Yi Ren, Zhiyi Yu, Xiaoyang Zeng, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A 65 nm Cryptographic Processor for High Speed Pairing Computation

Yang Li, Zhiyi Yu, Xiaoyang Zeng, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Motion artifact removal based on ICA for ambulatory ECG monitoring

Lijun Zhou, Xiaoyang Zeng, Jianwei Yang, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A full-custom design of AES SubByte module with signal independent power consumption

Liang Li, Xiaoyang Zeng, Jia Zhao, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks

Xiaoyang Zeng, Jun Han, Dabin Fang, 2013, 2013 IEEE Eighth International Conference on Networking, Architecture and Storage.

Countering power analysis attacks by exploiting characteristics of multicore processors

Zhang Zhang, Jianwei Yang, Xiaoyang Zeng, 2018, IEICE Electron. Express.

An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform

Shan Huang, Xiaoyang Zeng, Yao Zou, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

A low-cost cryptographic processor for security embedded system

Qing Li, Xiaoyang Zeng, Jia Zhao, 2008, 2008 Asia and South Pacific Design Automation Conference.

A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm

Lin Dai, Xiaoyang Zeng, Yao Zou, 2012, IEICE Trans. Inf. Syst..

A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms

Yang Li, Shuai Wang, Xiaoyang Zeng, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A high-performance platform-based SoC for information security

Min Wu, Yibo Fan, Xiaoyang Zeng, 2006, Asia and South Pacific Conference on Design Automation, 2006..

The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization

Yujie Huang, Yujie Cai, Yibo Fan, 2018, 2018 International SoC Design Conference (ISOCC).

Analysis of adaptive support-weight based stereo matching for hardware realization

Yang Li, Shuai Wang, Xiaoyang Zeng, 2011, 2011 9th IEEE International Conference on ASIC.

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture

Zhiyi Yu, Xiaoyang Zeng, Jun Han, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A configurable SoC design for information security

Yi Ren, Zhiyi Yu, Xiaoyang Zeng, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

An error-resilient wavelet-based ECG processor under voltage overscaling

Yi Li, Xiaoyang Zeng, Yicheng Zhang, 2014, 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings.

Robust and reliable frame synchronization method for DVB-S2 system

Xiaoyang Zeng, Xubin Chen, Wenhua Fan, 2010, 2010 Wireless Telecommunications Symposium (WTS).

A high utilization FPGA-based accelerator for variable-scale convolutional neural network

Xin Li, Yujie Cai, Xiaoyang Zeng, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels

Xiaoyang Zeng, Jun Han, Yanjie Peng, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A Low-cost and High-performance SoC Design for OMA DRM2 Applications

Xiaoyang Zeng, Jia Zhao, Jun Han, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Highly flexible WBAN transmit-receive system based on USRP

Xiaoyang Zeng, Tianchan Guan, Jun Han, 2013, 2013 IEEE 10th International Conference on ASIC.

A multi-core-based heterogeneous parallel turbo decoder

Zhiyi Yu, Zhang Zhang, Xin Cheng, 2017, IEICE Electron. Express.

A multi-task-oriented security processing architecture with powerful extensibility

Xiaoyang Zeng, Dan Cao, Jun Han, 2009, 2009 Asia and South Pacific Design Automation Conference.

Design of a high throughput configurable variable-length FFT processor based on switch network architecture

Xiaoyang Zeng, Jun Han, Renfeng Dou, 2013, 2013 IEEE 10th International Conference on ASIC.

Design of a single-ended cell based 65nm 32×32b 4R2W register file

Zhiyi Yu, Xiaoyang Zeng, Xingxing Zhang, 2011, 2011 9th IEEE International Conference on ASIC.

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation

Zhiyi Yu, Shuai Wang, Xiaoyang Zeng, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Prosthetic Modeling for Femoral Head Based on Ellipsoid Fitting

Bin Liu, Jun Han, De wei Zhao, 2009 .

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design

Zhiyi Yu, Xiaoyang Zeng, Jianwei Yang, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs

Xu Cheng, Yi Li, Xiaoyang Zeng, 2013, 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS).

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing

Yi Li, Xu Cheng, Zhiyi Yu, 2014, IEICE Electron. Express.

Exploration for energy-efficient ECC decoder of WBAN

Xiaoyang Zeng, Tianchan Guan, Jun Han, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A 16-Core Processor With Shared-Memory and Message-Passing Communications

Xu Cheng, Jiajie Zhang, Zhiyi Yu, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A hardware-efficient variable-length FFT processor for low-power applications

Xiaoyang Zeng, Jun Han, Renfeng Dou, 2013, 2013 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference.

A low power ASIP for precision configurable FFT processing

Xiaoyang Zeng, Yao Zou, Jun Han, 2012, Proceedings of The 2012 Asia Pacific Signal and Information Processing Association Annual Summit and Conference.

Optimal frame synchronization for DVB-S2

Chuan Wu, Li Qing, Xiaoyang Zeng, 2008, 2008 IEEE International Symposium on Circuits and Systems.

An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform

Xiaoyang Zeng, Yao Zou, Jun Han, 2013, IEEE Signal Processing Letters.

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP

Yi Li, Xu Cheng, Xiaoyang Zeng, 2013, 2013 IEEE 10th International Conference on ASIC.

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework

Xiaoyang Zeng, Jun Han, Yan Li, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC

Jun Han, Xinyu Qin, Xudong Liu, 2021, 2021 IEEE 14th International Conference on ASIC (ASICON).

MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications

Jun Tao, Xiaoyang Zeng, Xuyang Duan, 2021, IEEE Transactions on Biomedical Circuits and Systems.

An energy-efficient crypto-extension design for RISC-V

Jun Han, Xiaoyang Zeng, Xu Cheng, 2021, Microelectron. J..

A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning

Jun Han, Guozhu Xin, Yifan Zhao, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology

Xiaoyang Zeng, Jun Han, Tongde Li, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications

Xiaoyang Zeng, Jun Han, Xiaoyong Xue, 2021, IEEE Transactions on Circuits and Systems II: Express Briefs.

TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications

Mehdi B. Tahoori, Jun Han, Yan Li, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture

Xuyang Duan, Jun Han, Ruiqi Xie, 2021, 2021 IEEE 14th International Conference on ASIC (ASICON).

DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks

Jun Han, Jun Yin, Ruiqi Xie, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.