T. Tanizaki

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture

T. Gyohten, K. Dosaka, H. Noda, 2007, IEEE Journal of Solid-State Circuits.

A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write

T. Tanizaki, Y. Taito, M. Kinoshita, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

K. Dosaka, T. Tanizaki, K. Arimoto, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A multi matrix-processor core architecture for real-time image processing SoC

T. Gyohten, H. Noda, M. Nakajima, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

Practical low power design architecture for 256 Mb DRAM

T. Tanizaki, F. Morishita, T. Amano, 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

T. Gyohten, Kazutami Arimoto, T. Tanizaki, 2006, VLSIC 2006.

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

Takeshi Fujino, T. Tanizaki, F. Igaue, 2003 .

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

T. Gyohten, K. Dosaka, H. Noda, 2006, IEEE Journal of Solid-State Circuits.