Chetan Vudadha

发表

An Efficient Design Methodology for CNFET Based Ternary Logic Circuits

Chetan Vudadha, P. SaiPhaneendra, M. B. Srinivas, 2016, 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS).

A Novel Low Power Ternary Multiplier Design using CNFETs

Chetan Vudadha, Harita Sirugudi, Sharvani Gadgil, 2020, 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID).

Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs

Chetan Vudadha, M. B. Srinivas, M. Srinivas, 2018, IEEE Transactions on Nanotechnology.

Design of Prefix-Based Optimal Reversible Comparator

Chetan Vudadha, P. SaiPhaneendra, Syed Ershad Ahmed, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Multiplexer Based Design for Ternary Logic Circuits

Chetan Vudadha, M. B. Srinivas, V. Sreehari, 2012 .

Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach

Chetan Vudadha, Sharvani Gadgil, C. Vudadha, 2020, IEEE Transactions on Nanotechnology.

Energy efficient design of CNFET-based multi-digit ternary adders

Chetan Vudadha, M. B. Srinivas, Sai Phaneendra Parlapalli, 2018, Microelectron. J..

Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits

Chetan Vudadha, M. B. Srinivas, P. Sai Phaneendra, 2018, IEEE Transactions on Nanotechnology.

Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers

Chetan Vudadha, M. B. Srinivas, Saurabh Agrawal, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

CNFET based ternary magnitude comparator

Chetan Vudadha, P. SaiPhaneendra, Sreehari Veeramachaneni, 2012, 2012 International Symposium on Communications and Information Technologies (ISCIT).

Design Methodologies for Ternary Logic Circuits

Chetan Vudadha, M. B. Srinivas, M. Srinivas, 2018, 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL).

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths

Chetan Vudadha, P. SaiPhaneendra, Syed Ershad Ahmed, 2011, 2011 11th International Symposium on Communications & Information Technologies (ISCIT).

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders

Chetan Vudadha, P. SaiPhaneendra, Syed Ershad Ahmed, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

A New Design of an N-Bit Reversible Arithmetic Logic Unit

Chetan Vudadha, P. SaiPhaneendra, Sreehari Veeramachaneni, 2014, 2014 Fifth International Symposium on Electronic System Design.

Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs

Chetan Vudadha, Sharvani Gadgil, Poojan Patel, 2019, 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS).

Design of Ternary Logic Circuits Using CNFETs

Chetan Vudadha, M. B. Srinivas, 2018 .

Optimizing the Reversible Circuits Using Complementary Control Line Transformation

Chetan Vudadha, M. B. Srinivas, Sai Phaneendra Parlapalli, 2017, RC.

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs

Chetan Vudadha, P. SaiPhaneendra, Syed Ershad Ahmed, 2012, 2012 25th International Conference on VLSI Design.

An ESOP Based Cube Decomposition Technique for Reversible Circuits

Chetan Vudadha, M. B. Srinivas, Sai Phaneendra Parlapalli, 2017, RC.

An Optimized Design of Reversible Quantum Comparator

Chetan Vudadha, P. SaiPhaneendra, Sreehari Veeramachaneni, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design

Chetan Vudadha, P. Veda Bhanu, J Soumya, 2020, ISCAS.

Optimization of Reversible Circuits Using Gate Pair Classification

Chetan Vudadha, M. B. Srinivas, P. Sai Phaneendra, 2021, SN Computer Science.

Non-linear partitioning for decimal logarithm approximation

Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas, 2011, 2011 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics.

2:1 Multiplexer based design for ternary logic circuits

Chetan Vudadha, P. Sai Phaneendra, Sowmya Katragadda, 2013, 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).