Weirong Jiang

发表

A Lightweight Secure SIP Model for End-to-End Communication

Weirong Jiang, 2005 .

Data Structure Optimization of AS_PATH in BGP

Weirong Jiang, Weirong Jiang, 2005, ICCNMC.

A Framework for Security-Enhanced Peer-to-Peer Applications in Mobile Cellular Networks

Weirong Jiang, Shuping Liu, Shushan Zhao, 2011, Int. J. Commun. Netw. Syst. Sci..

FEACAN: Front-end acceleration for content-aware network processing

Viktor K. Prasanna, Kai Wang, Yibo Xue, 2011, 2011 Proceedings IEEE INFOCOM.

High-Speed Packet Processing using Reconfigurable Computing

Gordon J. Brebner, Weirong Jiang, G. Brebner, 2014, IEEE Micro.

Compact architecture for high-throughput regular expression matching on FPGA

Viktor K. Prasanna, Weirong Jiang, Yi-Hua Edward Yang, 2008, ANCS '08.

Practical Multituple Packet Classification Using Dynamic Discrete Bit Selection

Baohua Yang, Yibo Xue, Weirong Jiang, 2014, IEEE Transactions on Computers.

A Scalable and Modular Architecture for High-Performance Packet Classification

Viktor K. Prasanna, Thilan Ganegedara, Weirong Jiang, 2014, IEEE Transactions on Parallel and Distributed Systems.

ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification

Xiang Wang, Yaxuan Qi, Weirong Jiang, 2012, 2012 IEEE 20th Annual Symposium on High-Performance Interconnects.

Multi-dimensional packet classification on FPGA: 100 Gbps and beyond

Viktor K. Prasanna, Yaxuan Qi, Weirong Jiang, 2010, 2010 International Conference on Field-Programmable Technology.

Field-split parallel architecture for high performance multi-match packet classification using FPGAs

Viktor K. Prasanna, Weirong Jiang, V. Prasanna, 2009, SPAA '09.

A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification

Viktor K. Prasanna, Weirong Jiang, V. Prasanna, 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.

Large-scale wire-speed packet classification on FPGAs

Viktor K. Prasanna, Weirong Jiang, V. Prasanna, 2009, FPGA '09.

Scalable multi-pipeline architecture for high performance multi-pattern string matching

Viktor K. Prasanna, Weirong Jiang, Yi-Hua Edward Yang, 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS).

The effects of advanced information feedback strategies in FI model

Zhengtao Xiang, Wei Jian, Yufeng Chen, 2011, 2011 International Conference on Multimedia Technology.

An Improved Information Feedback Strategy for Symmetrical Two-Route Traffic Flow Model

Wei Jian, Zhengtao Xiang, Yubing Jian, 2011, 2011 UkSim 13th International Conference on Computer Modelling and Simulation.

An improved AOMDV routing protocol for V2V communication

Zhengtao Xiang, Wei Jian, Yufeng Chen, 2009, 2009 IEEE Intelligent Vehicles Symposium.

Parallel IP lookup using multiple SRAM-based pipelines

Viktor K. Prasanna, Weirong Jiang, V. Prasanna, 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

Energy-Efficient Multi-Pipeline Architecture for Terabit Packet Classification

Viktor K. Prasanna, Weirong Jiang, V. Prasanna, 2009, GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference.

Load-aware bidirectional pipeline construction for terabit IP forwarding

Yun Zhu, Weirong Jiang, Weirong Jiang, 2009, 2009 43rd Annual Conference on Information Sciences and Systems.

Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup

Viktor K. Prasanna, Weirong Jiang, Qingbo Wang, 2008, IEEE INFOCOM 2008 - The 27th Conference on Computer Communications.

FRuG: A benchmark for packet forwarding in future networks

Viktor K. Prasanna, Thilan Ganegedara, Weirong Jiang, 2010, International Performance Computing and Communications Conference.

A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms

Viktor K. Prasanna, Shijie Zhou, Weirong Jiang, 2014, 2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC).