Satish Sivaswamy

Performance driven routing for modern FPGAs invited paper

Parivallal Kannan, Satish Sivaswamy, S. Sivaswamy, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

HARP: hard-wired routing pattern FPGAs

Kia Bazargan, Gang Wang, Ryan Kastner, 2005, FPGA '05.

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Gang Wang, Kia Bazargan, Ryan Kastner, 2005 .

Variation-aware routing for FPGAs

Kia Bazargan, Satish Sivaswamy, K. Bazargan, 2007, FPGA '07.

Architecture and cad techniques for optimizing fpgas and reliability of integrated circuits

Satish Sivaswamy, Bazargan Kiarash, Satish Sivaswamy, 2009 .

Estimation and optimization of reliability of noisy digital circuits

Kia Bazargan, Marc D. Riedel, Satish Sivaswamy, 2009, 2009 10th International Symposium on Quality Electronic Design.

Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs

Kia Bazargan, Satish Sivaswamy, K. Bazargan, 2008, TRETS.

Statistical Analysis and Design of HARP FPGAs

Kia Bazargan, Gang Wang, Ryan Kastner, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Statistical Generic and Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs

Kia Bazargan, Satish Sivaswamy, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Statistical Analysis and Design of HARP Routing Pattern FPGAs

Gang Wang, Kia Bazargan, Ryan Kastner, 2005 .