N. Lourenço

发表

LAYGEN – Automatic Analog ICs Layout Generator

N. Horta, N. Lourenço, 2007 .

Nuno Horta, Nuno Lourenco, João P. S. Rosa, 2019, Using Artificial Neural Networks for Analog Integrated Circuit Design Automation.

Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test

Engin Afacan, Nuno Lourenço, Gunhan Dundar, 2021, Integr..

State-of-the-Art on Automatic Analog IC Sizing

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2014 .

Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2013, DoCEIS.

PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs

N. Horta, F. Fernández, R. Castro-López, 2023, IEEE Journal of Microwaves.

Background and State-of-the-Art

Ricardo Povoa, Nuno Horta, Joao Goes, 2018, Tunable Low-Power Low-Noise Amplifier for Healthcare Applications.

A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2013, 2013 IEEE Congress on Evolutionary Computation.

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Proposed Design and Implementation

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2021 .

GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation

Nuno Horta, Nuno Lourenço, N. Horta, 2012, GECCO '12.

Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2016, Integr..

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2016, Integr..

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools

Rui P. Martins, Nuno Horta, Pui-In Mak, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications

Ricardo Povoa, Joao Goes, Nuno Horta, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Current-flow and current-density-aware multi-objective optimization of analog IC placement

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2016, Integr..

Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2016 .

Electromigration-aware analog Router with multilayer multiport terminal structures

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2014, Integr..

Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Laygen - An evolutionary approach to automatic analog IC layout generation

Nuno Horta, Nuno Lourenço, N. Horta, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

Routing analog ICs using a multi-objective multi-constraint evolutionary approach

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2014 .

Analog Circuit Design Based on Robust POFs Using an Enhanced MOEA with SVM Models

Nuno Horta, Manuel Barros, Nuno Lourenço, 2013 .

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications

Pui-In Mak, Nuno Horta, Rui P. Martins, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing

Nuno Horta, Fábio Passos, Günhan Dündar, 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

On the Exploration of Promising Analog IC Designs via Artificial Neural Networks

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2018, 2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing

Ricardo Povoa, Nuno Horta, Nuno Lourenco, 2021, Eng. Appl. Artif. Intell..

Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2015, Expert Syst. Appl..

Analog IC placement using absolute coordinates and a hierarchical combination of Pareto optimal fronts

Nuno Horta, Ricardo Martins, Nuno Lourenco, 2015, 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

Using ANNs to Size Analog Integrated Circuits

Nuno Horta, Ricardo Martins, Nuno Lourenco, 2019 .

DeepPlacer: A custom integrated OpAmp placement tool using deep models

N. Horta, N. Lourenço, R. Martins, 2021, Appl. Soft Comput..

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

N. Horta, F. Fernández, F. Passos, 2021, IEEE Access.

FUZYE: A Fuzzy ${c}$ -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms

Ricardo Povoa, Nuno Horta, João Paulo Carvalho, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology

Francisco V. Fernández, Ricardo Povoa, Nuno Horta, 2018, Integr..

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization

Francisco V. Fernández, Ricardo Povoa, Nuno Horta, 2017, 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization

N. Horta, P. Alves, N. Lourenço, 2022, Electronics.

Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation

N. Horta, N. Lourenço, R. Martins, 2022, Electronics.

On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects

Nuno Horta, Ricardo Martins, Nuno Lourenço, 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender

António Gusmão, Ricardo Povoa, Nuno Horta, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

Artificial Neural Networks as an Alternative for Automatic Analog IC Placement

Nuno Horta, Ricardo Martins, Nuno Lourenço, 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving

N. Horta, J. Goes, R. Martins, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement

Joao Goes, Ricardo Martins, Nuno Lourenço, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 23.5–32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology

N. Horta, J. Vaz, N. Lourenço, 2023, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design.

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models

N. Horta, J. Vaz, N. Lourenço, 2023, 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC).

In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization

Nuno Lourenço, Ricardo Martins, Luís Mendes, 2021, IEEE Access.

Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Multi-port multi-terminal analog router based on an evolutionary optimization kernel

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2013, 2013 IEEE Congress on Evolutionary Computation.

Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations

Ricardo Povoa, Nuno Horta, Nuno Lourenço, 2016, 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Multi-objective Optimization Kernel

Nuno Horta, Nuno Lourenço, Ricardo Martins, 2017 .

Previous Works on Automated Analog IC Sizing

Nuno Horta, Nuno Lourenço, Ricardo Lourenço, 2015 .

AIDA-PEx: Accurate parasitic extraction for layout-aware analog integrated circuit sizing

Nuno Horta, Ricardo Martins, Nuno Lourenco, 2015, 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).