Daniel Ziener

发表

New Directions for FPGA IP Core Watermarking and Identification

J. Teich, Daniel Ziener, 2010 .

Verifying the Authorship of Embedded IP Cores : Watermarking and Core Identification Techniques

J. Teich, Daniel Ziener, 2011 .

Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration

Jürgen Teich, Daniel Ziener, Christopher Dennl, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs

Daniel Ziener, Daniel Ziener, 2010 .

Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs

Jürgen Teich, Daniel Ziener, J. Teich, 2009, Int. J. Auton. Adapt. Commun. Syst..

Throughput Optimizations for FPGA-based Deep Neural Network Inference pdf

Daniel Ziener, Thorbjörn Posewsky, Daniel Ziener, 2018, Microprocess. Microsystems.

A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks

Daniel Ziener, Thorbjörn Posewsky, Daniel Ziener, 2018, ARCS.

Efficient deep neural network acceleration through FPGA-based batch processing

Daniel Ziener, Thorbjörn Posewsky, Daniel Ziener, 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration

Daniel Ziener, Nikolaos S. Alachiotis, Nikolaos Alachiotis, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

An FPGA implementation of a threat-based strategy for Connect6

Jürgen Teich, Moritz Mühlenthaler, Daniel Ziener, 2011, 2011 International Conference on Field-Programmable Technology.

Power Signature Watermarking of IP Cores for FPGAs

Jürgen Teich, Daniel Ziener, J. Teich, 2008, J. Signal Process. Syst..

FPGAs for Software Programmers

Dirk Koch, Daniel Ziener, Frank Hannig, 2016 .

FPGA Versus Software Programming: Why, When, and How?

Dirk Koch, Daniel Ziener, Frank Hannig, 2016, FPGAs for Software Programmers.

Identifying FPGA IP-Cores Based on Lookup Table Content Analysis

Jürgen Teich, Daniel Ziener, Stefan Assmus, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning

Jürgen Teich, Daniel Ziener, Bernhard Schmidt, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

FPGA-Based Dynamically Reconfigurable SQL Query Processing

Jürgen Teich, Andreas Becher, Daniel Ziener, 2016, ACM Trans. Reconfigurable Technol. Syst..

Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration

Benjamin Hettwer, Daniel Ziener, Ali Asghar, 2021, ARC.

Configuration Tampering of BRAM-based AES Implementations on FPGAs

Jürgen Teich, Daniel Ziener, Jutta Pirkl, 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

Daniel Ziener, Nikolaos S. Alachiotis, Nikolaos Alachiotis, 2021, Journal of Low Power Electronics and Applications.

Partial reconfiguration on FPGAs in practice — Tools and applications

Jürgen Teich, Walter Stechele, Jim Tørresen, 2012, ARCS 2012.

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs

Jürgen Teich, Stefan Wildermann, Andreas Becher, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

Jürgen Teich, Andreas Becher, Daniel Ziener, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Symbolic system-level design methodology for multi-mode reconfigurable systems

Jürgen Teich, Stefan Wildermann, Daniel Ziener, 2013, Des. Autom. Embed. Syst..

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library

Jürgen Teich, Daniel Ziener, Christopher Dennl, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

Throughput Optimizations for FPGA-based Deep Neural Network Inference

Daniel Ziener, Thorbjörn Posewsky, 2018, Microprocess. Microsystems.