C. Wolinski

Area and Recon ! guration Time Minimization of the Communication Network in Regular 2 D Recon ! gurable Architectures

J. Teich, Frank Hannig, C. Wolinski, 2008 .

New Results - Study of applications

François Charot, Patrice Quinton, Laurent Amsaleg, 2007 .

A SYNCHRONOUS APPROACH FOR HARDWARE DESIGN

Jean-Christophe Le Lann, F. Bodin, P. Guernic, 1997 .

Hierarchical conditional dependency graphs for mutual exclusiveness identification

Apostolos A. Kountouris, Christophe Wolinski, A. Kountouris, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

High level pre-synthesis optimization steps using hierarchical conditional dependency graphs

Apostolos A. Kountouris, Christophe Wolinski, A. Kountouris, 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

Combined scheduling and instruction selection for processors with reconfigurable cell fabric

Krzysztof Kuchcinski, Antoine Floch, Christophe Wolinski, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

A constraints programming approach to communication scheduling on SoPC architectures

Krzysztof Kuchcinski, Maya Gokhale, Christophe Wolinski, 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications

François Charot, Christophe Wolinski, Fabien Demangel, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures

Jürgen Teich, Krzysztof Kuchcinski, Frank Hannig, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures

Jürgen Teich, Krzysztof Kuchcinski, Frank Hannig, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures

Jürgen Teich, Krzysztof Kuchcinski, Frank Hannig, 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.

Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation

François Charot, Krzysztof Kuchcinski, Kevin J. M. Martin, 2012, TRETS.