S. Veeraraghavan

发表

PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations

Colin C. McAndrew, W. Wu, Xin Li, 2009 .

Experimental studies and performance evaluation of solar PV powered BLDC motor drive with an integrated MPPT in fan applications

Ashok Jhunjhunwala, S. Veeraraghavan, Krishna Vasudevan, 2014, 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC).

A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

P. Abramowitz, J. Conner, M. Woo, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Optimization of a Pan Cake Coil Dimensions for Flaw Sizing in Pipes: Eddy Current Benchmark Problem — 3

Krishnan Balasubramaniam, S. Veeraraghavan, 2004 .

Performance Evaluation of Solar Photo Voltaic Modules Under Field Conditions Through a Quick Diagnostic Tool

S. Veeraraghavan, M. Kumaravel, C. R. Jeevandoss, 2008 .

Inter-leaved filter structure using IMM for handling measurement association uncertainty in high clutter density

S. Veeraraghavan, M. Sharma, M. J. Sagayaraj, 2006 .

A physics-based, dynamic thermal impedance model for SOI MOSFET's

Robert Fox, S. Veeraraghavan, J. S. Brodsky, 1997 .

A high performance 1.5 V, 0.10 /spl mu/m gate length CMOS technology with scaled copper metallization

S. Veeraraghavan, M. Kling, C. Feng, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A surface potential-based compact model of n-MOSFET gate-tunneling current

G. Gildenblat, S. Veeraraghavan, G.O. Workman, 2004, IEEE Transactions on Electron Devices.

Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors

S. Veeraraghavan, D. Tekleab, K. Loiko, 2007, 2007 IEEE International SOI Conference.

Inline monitoring of multi-level dual inlaid copper interconnect technologies

S. Veeraraghavan, S. Venkatesan, John Mendonca, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

S. Veeraraghavan, F. Gamiz, G.O. Workman, 2006, IEEE Transactions on Electron Devices.

Short-channel effects in SOI MOSFETs

S. Veeraraghavan, Jerry G. Fossum, J. Fossum, 1989 .

Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay

S. Veeraraghavan, N. Bhat, V. Misra, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).