D. Furey

Asynchronous Circuit Design via Automated Petri Net Generation

M. B. Josephs, D. Furey, 2022 .

A Programming Approach to the Design of Asynchronous Logic Blocks

Mark B. Josephs, M. B. Josephs, Dennis P. Furey, 2002, Concurrency and Hardware Design.

Delay-insensitive interface specification and synthesis

M. B. Josephs, D. Furey, M.B. Josephs, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Simulation, synthesis, and verification of pipelined asynchronous VLSI circuits

Neil W. Bergmann, Dennis Furey, N. Bergmann, 1997, TENCON '97 Brisbane - Australia. Proceedings of IEEE TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications (Cat. No.97CH36162).

Verification and implementation of delay-insensitive processes in restrictive environments

Hemangee K. Kapoor, Mark B. Josephs, M. B. Josephs, 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..