Takahiro Onai

发表

Simplified Distribution Base Resistance Model in Self-Aligned Bipolar Transistors (Special Issue on Microelectronic Test Structure)

Katsuyoshi Washio, M. Tanabe, Hiromi Shimamoto, 1996 .

High-Frequency, Low-Noise Si Bipolar Transistor Fabricated Using Self-Aligned Metal/IDP Technology

Katsuyoshi Washio, M. Tanabe, Hiromi Shimamoto, 1999 .

Outlook for Advanced Semiconductor Process and Manufacturing Technologies

Takahiro Onai, Hiroshi Miyazaki, 2003 .

Test Structure and Experimental Analysis of Emitter-Base Reverse Voltage Stress Degradation in Self-Aligned Bipolar Transistors (Special Issue on Microelectronic Test Structure)

Katsuyoshi Washio, M. Tanabe, Hiromi Shimamoto, 1996 .

Process and device technologies for high speed self-aligned bipolar transistors

Noriyuki Homma, Katsuyoshi Washio, Takahiro Onai, 1995 .

A SiGe HBT IC CHIPSET for40-Gb/s OPTICAL TRANSMISSION SYSTEMS

Toru Masuda, Katsuyoshi Washio, M. Tanabe, 2003 .

Self-Aligned Metal/IDP Si Bipolar Technology with 12-ps ECL and 45-GHz Dynamic Frequency Divider

Katsuyoshi Washio, Takahiro Onai, Masamichi Tanabe, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

Improved theory for remote-charge-scattering-limited mobility in metal–oxide–semiconductor transistors

Kazuyoshi Torii, Takahiro Onai, K. Torii, 2002 .

Self-aligned complementary bipolar technology for low-power dissipation and ultra-high-speed LSIs

Youji Idei, Katsuyoshi Washio, M. Tanabe, 1995 .

SPOTEC-a sub-10- mu m/sup 2/ bipolar transistor structure using fully self-aligned sidewall polycide base technology

Fumio Murai, Tokuo Kure, Takahiro Onai, 1991, International Electron Devices Meeting 1991 [Technical Digest].

SEPIA: a new isolation structure for soft-error-immune LSIs

Noriyuki Homma, Takahiro Onai, Tohru Nakamura, 1993 .

SA 19.6: 95GHz fT Self-Aligned Selective Epitaxial SiGe HBT with SNll Electrodes

K. Washio, M. Tanabe, Hiromi Shimamoto, 1998 .

Ultra-low-power and high-speed SiGe base bipolar transistors for wireless telecommunication systems

Katsuyoshi Washio, M. Tanabe, Hiromi Shimamoto, 1998 .

Soft-error immune switched-load-resistor memory cell

Kazuo Nakazato, Noriyuki Homma, Takahiro Onai, 1987, 1987 Symposium on VLSI Technology.

Silicon light-emitting transistor for on-chip optical interconnection

Nobuyuki Sugii, Digh Hisamoto, Kazuyoshi Torii, 2006 .

Lamp-heated rapid vapor-phase doping technology for 100-GHz Si bipolar transistors

Katsuyoshi Washio, M. Tanabe, Takahiro Onai, 1996, Proceedings of the 1996 BIPOLAR/BiCMOS Circuits and Technology Meeting.

Self-aligned metal/IDP Si bipolar technology featuring 14 ps/70 GHz

Katsuyoshi Washio, M. Tanabe, Takahiro Onai, 1995, Proceedings of International Electron Devices Meeting.

Ultra-small high-speed bipolar transistor with sidewall silicide technology

Yoichi Tamaki, Noriyuki Homma, Takahiro Onai, 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.

An NPN 30 GHz, PNP 32 GHz f/sub T/ complementary bipolar technology

Katsuyoshi Washio, M. Tanabe, Hiromi Shimamoto, 1993, Proceedings of IEEE International Electron Devices Meeting.

Remote-charge-scattering limited mobility in field-effect transistors with SiO2 and Al2O3∕SiO2 gate stacks

Yasuhiro Shimamoto, Osamu Tonomura, Matty Caymax, 2005 .