U. Ko

Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

L. Bouetel, C. Raibaut, H. Mair, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

Characterization and design of a low-power, high-performance cache architecture

U. Ko, P. T. Balsara, P. Balsara, 1995, 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.

A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations

H. Mair, P. Royannez, D. Scott, 2007, 2007 IEEE Symposium on VLSI Circuits.

Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor

L. Bouetel, C. Raibaut, H. Mair, 2006, 2006 IEEE International Conference on IC Design and Technology.

A self-timed method to minimize spurious transitions in low power CMOS circuits

U. Ko, P. T. Balsara, W. Lee, 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

A 30-ps jitter, 3.6-/spl mu/s locking, 3.3-volt digital PLL for CMOS gate arrays

U. Ko, S. A. Wichman, S. Castrianni, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.