H. Araki

Process technologies for a 16 ns high speed 1 Mb CMOS EPROM

K. Narita, N. Matsukawa, H. Araki, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

PRD-based global-mean-time signaling for high-speed chip-to-chip communications

H. Tamura, M. Taguchi, H. Araki, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

A 16 ns 1 Mb CMOS EPROM

K. Narita, S. Tanaka, N. Matsukawa, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

A new MOSFETs degradation induced by gate current in off-state condition

Y. Kaneko, K. Narita, H. Araki, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM

T. Watanabe, H. Oodaira, Y. Iwata, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

Reliability study of thin inter-poly dielectrics for non-volatile memory application

H. Araki, Kuniyoshi Yoshikawa, Y. Ohshima, 1990, 28th Annual Proceedings on Reliability Physics Symposium.

ONO inter-poly dielectric scaling for nonvolatile memory applications

H. Araki, Kuniyoshi Yoshikawa, Y. Ohshima, 1991 .