R. Iskander

Study of technology migration on 2nd generation current conveyors performance

H. F. Ragaie, R. Iskander, S. Kayed, 2001, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257).

Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors

R. Iskander, M.-M. Louerat, A. Kaiser, 2006, 2006 Ph.D. Research in Microelectronics and Electronics.

Design space exploration for analog IPS using CAIRO+

R. Iskander, M.-M. Louerat, A. Kaiser, 2004, International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04..

Knowledge-aware synthesis using hierarchical graph-based sizing and biasing

R. Iskander, M.-M. Louerat, A. Kaiser, 2007, 2007 IEEE Northeast Workshop on Circuits and Systems.

Analog circuits sizing using the fixed point iteration algorithm with transistor compact models

R. Iskander, F. Javid, F. Durbin, 2012, Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012.

Computing systematic offset in amplifiers using hierarchical graph-based sizing and biasing

R. Iskander, M.-M. Louerat, A. Kaiser, 2007, 2007 Internatonal Conference on Microelectronics.

Automatic biasing point extraction and design plan generation for analog IPs

R. Iskander, M.M. Louerat, A. Kaiser, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..