Vikram Arkalgud Chandrasetty

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Motion Estimation Technique for H.264 Advanced Video Coder

Vikram Arkalgud Chandrasetty, 2010 .

An area efficient LDPC decoder using a reduced complexity min-sum algorithm

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, S. M. Aziz, 2012, Integr..

Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes pdf

Sarah J. Johnson, Vikram Arkalgud Chandrasetty, Gottfried Lechner, 2013, ArXiv.

LDPC decoding algorithms

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2018 .

A reduced complexity message passing algorithm with improved performance for LDPC decoding

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, S. M. Aziz, 2009, 2009 12th International Conference on Computers and Information Technology.

Analysis of performance and implementation complexity of simplified algorithms for decoding Low-Density Parity-Check codes

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, S. M. Aziz, 2010, 2010 IEEE Globecom Workshops.

Resource efficient LDPC decoders for multimedia communication pdf

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2015, Integr..

Chapter 8 – Prospective LDPC applications

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2018 .

FPGA Application Design

Vikram Arkalgud Chandrasetty, 2011 .

FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, S. M. Aziz, 2010, 2010 Second International Conference on Computer Research and Development.

LDPC decoders in multimedia communication

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2018 .

VLSI Design - A Practical Guide for FPGA and ASIC Implementations

Vikram Arkalgud Chandrasetty, 2011, Springer Briefs in Electrical and Computer Engineering.

Hardware implementation of LDPC decoders

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2018 .

Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes

Sarah J. Johnson, Vikram Arkalgud Chandrasetty, Gottfried Lechner, 2014, IET Commun..

A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2012, J. Networks.

Analog and Mixed Signal Design

Vikram Arkalgud Chandrasetty, 2011 .

FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, S. M. Aziz, 2011, J. Networks.

CMOS Digital Design

Vikram Arkalgud Chandrasetty, 2011 .

Overview of LDPC codes

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, S. M. Aziz, 2018 .

Construction of a multi-level Hierarchical Quasi-Cyclic matrix with layered permutation for partially-parallel LDPC decoders

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, S. M. Aziz, 2010, 2010 13th International Conference on Computer and Information Technology (ICCIT).

LDPC decoder architectures

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2018 .

Repeat-accumulate codes for reconciliation in continuous variable quantum key distribution

Sarah J. Johnson, Vikram Arkalgud Chandrasetty, Andrew M. Lance, 2015, 2016 Australian Communications Theory Workshop (AusCTW).

A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2011, 2011 IEEE International Conference on Multimedia and Expo.

Structure and flexibility of LDPC codes

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz, 2018 .