Jiang Chau Wang

发表

DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm

Ernesto Villegas Castillo, Gabriele Miorandi, Jiang Chau Wang, 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

Optimized cube expansion with binary decision diagrams and expansion graphs for logic minimization

Jiang Chau Wang, 1993 .

On TLM traffic accuracy: A multifractal perspective

Jiang Chau Wang, Jose Eduardo Chiarelli Bueno Filho, 2018, 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS).

Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor

Jiang Chau Wang, Marius Strum, Edgar Leonardo Romero Tobar, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

Mixed signal verification to avoid integration mismatch in complex SoCs

Jiang Chau Wang, Vinicius Martins, Jerson Paulo Guex, 2017, 2017 18th IEEE Latin American Test Symposium (LATS).

Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification

Jiang Chau Wang, Marius Strum, Edgar Leonardo Romero Tobar, 2013, J. Electron. Test..

Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS

Jiang Chau Wang, Marius Strum, Raul Acosta Hernandez, 2015, 2015 16th Latin-American Test Symposium (LATS).

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

A Recursive High Level Synthesis System

Jiang Chau Wang, Marius Strum, M. Y. Teruya, 1997 .

Workload and task characterization based on operation modes timing analysis

Jiang Chau Wang, Marius Strum, Jorge Gonzalez, 2012, 2012 IEEE International SOC Conference.

A System-level Performance Evaluation Methodology for Netwrok Processors Based on Network Calculus Analytical Modeling

Jiang Chau Wang, Marius Strum, Frederico De Faria, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection

Martha Johanna Sepúlveda, Jiang Chau Wang, Ricardo Pires, 2010, Trans. Comput. Sci..

Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2013, 2013 8th IEEE Design and Test Symposium.

Hybrid-on-chip communication architecture for dynamic MP-SoC protection

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2012, 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI).

Dynamic NoC-based architecture for MPSoC security implementation

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2011, SBCCI '11.

Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems

Jiang Chau Wang, Marius Strum, Jonas Gomes Filho, 2015, Int. J. Reconfigurable Comput..

Miriã_SI: A Tool for the Synthesis of Speed-Independent Multi Burst-Mode Controllers

Jiang Chau Wang, Duarte Lopes de Oliveira, Marius Strum, 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training

Jiang Chau Wang, Marius Strum, Raul Acosta Hernandez, 2009, 2009 International Joint Conference on Neural Networks.

A PD-based methodology to enhance efficiency in testbenches with random stimulation

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2009, SBCCI.

QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2012, Int. J. Reconfigurable Comput..

The LRD traffic impact on the NoC-based SoCs

Martha Johanna Sepúlveda, Jiang Chau Wang, Ricardo Pires, 2010, SBCCI '10.

PrOCov: Probabilistic output coverage model

Jiang Chau Wang, Marius Strum, Joel Ivan Munoz Quispe, 2013, 2013 14th Latin American Test Workshop - LATW.

The functional verification of a satellite transponder

Jiang Chau Wang, Vinicius Martins, Jerson Paulo Guex, 2018, 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS).

A methodology for minimum area cellular automata generation

Jiang Chau Wang, Marius Strum, José Roberto de A. Amazonas, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Formal equivalence checking between high-level and RTL hardware designs

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2013, 2013 14th Latin American Test Workshop - LATW.

Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems

Jiang Chau Wang, Duarte Lopes de Oliveira, Marius Strum, 2003, Microelectron. Reliab..

Collective test generation and test set compaction

Jiang Chau Wang, Edward P. Stabler, E. Stabler, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Architectural Transformations for Hierarchical Algorithmic Descriptions

Jiang Chau Wang, Marius Strum, Marcio Yukio Teruya, 1999, VLSI.

A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2015, J. Electron. Test..

A dynamically reconfigurable Bluetooth Base Band Unit

Jiang Chau Wang, Marius Strum, John Esquiagola, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Multifractal on-chip traffic generation under TLM

Jiang Chau Wang, Jose Eduardo Chiarelli Bueno Filho, 2017, 2017 30th IEEE International System-on-Chip Conference (SOCC).

Transformations for functional modules in hierarchical high level synthesis

Jiang Chau Wang, Marius Strum, A A Jerraya, 1997 .

A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling

Jiang Chau Wang, Marius Strum, Edgar Leonardo Romero Tobar, 2011, J. Electron. Test..

Scenario-Aware Workload Characterization Based on a Max-Plus Linear Representation

Jiang Chau Wang, Gustavo Patino Alvarez, J. Wang, 2016, FORMATS.

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2012, GECCO '12.

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost

Davide Bertozzi, Ernesto Villegas Castillo, Gabriele Miorandi, 2015, ARC.

A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs

Jiang Chau Wang, Marius Strum, Carlos Ivan Castro Marquez, 2014, 2014 15th Latin American Test Workshop - LATW.

Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost

Davide Bertozzi, Ernesto Villegas Castillo, Gabriele Miorandi, 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

A strategy for recursive high level synthesis

Jiang Chau Wang, Marius Strum, A A Jerraya, 1997 .

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping

Martha Johanna Sepúlveda, Guy Gogniat, Jiang Chau Wang, 2013, GECCO '13 Companion.