T. Eudes

Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

B. Ravelo, T. Eudes, R. Alhayek, 2013 .

Z/Y/T/S-Matrices’ Modelling of Symmetric SIMO Structure Based on Elementary Distributed RLC-Cell

B. Ravelo, T. Eudes, 2019 .

Distributed model of two-level asymmetrical PCB interconnect tree

B. Ravelo, T. Lacrevaz, B. Flechet, 2013, 2013 International Symposium on Electromagnetic Compatibility.

Experimental Validations of a Simple PCB Interconnect Model for High-Rate Signal Integrity

B. Ravelo, A. Louis, T. Eudes, 2012, IEEE Transactions on Electromagnetic Compatibility.

Cancellation of Delays in the High-Rate Interconnects with UWB NGD Active Cells

Blaise Ravelo, Thomas Eudes, B. Ravelo, 2011 .

Electrical performance modeling of unbalanced comb tree networks on advanced PCB interconnects for high-rate clock signal distribution

Thierry Lacrevaz, Bernard Flechet, Blaise Ravelo, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Z/Y/T/S-Matrices’ Analysis of Non-symmetric SIMO Tree Based on Elementary Distributed Element

B. Ravelo, T. Lacrevaz, B. Fléchet, 2019 .

Fast estimation of high-speed signal integrity for coupled PCB interconnects

Thierry Lacrevaz, Bernard Flechet, Blaise Ravelo, 2013, 2013 17th IEEE Workshop on Signal and Power Integrity.