Jean-Luc Nagel

发表

Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures

Christian Schuster, Pierre-André Farine, Jean-Luc Nagel, 2004, PATMOS.

Ultra low power microelectronics for wearable and medical devices

Jean-Luc Nagel, Olivier Chételat, Marc Pons, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications

Jean-Luc Nagel, Pierre-François Ruedi, Claude Arm, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Trends in Design Methods for Complex Heterogeneous Systems

Jean-Luc Nagel, Christian Piguet, Jean-Marc Masgonty, 2012 .

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth

Christian Schuster, Pierre-André Farine, Jean-Luc Nagel, 2005, J. Low Power Electron..

A low-power VLSI architecture for face verification using elastic graph matching

Jean-Luc Nagel, Fausto Pellandini, Michael Ansorge, 2002, 2002 11th European Signal Processing Conference.

Smart low-power CMOS cameras for 3G mobile communicators

Jean-Luc Nagel, Fausto Pellandini, Peter Seitz, 2002, ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605).

Architectural and technology influence on the optimal total power consumption

Christian Schuster, Pierre-André Farine, Jean-Luc Nagel, 2006, DATE.

Low-Power Heterogeneous Systems-on-Chips

Jean-Luc Nagel, Christian Piguet, Jean-Marc Masgonty, 2008, J. Low Power Electron..

A multiscale morphological coprocessor for low-power face authentication

Jean-Luc Nagel, Fausto Pellandini, Michael Ansorge, 2002, 2002 11th European Signal Processing Conference.

Static and Dynamic Power Reduction by Architecture Selection

Christian Schuster, Jean-Luc Nagel, Christian Piguet, 2006, PATMOS.

Energy parsimonious circuit design through probabilistic pruning

Lingamneni Avinash, Krishna V. Palem, Jean-Luc Nagel, 2011, 2011 Design, Automation & Test in Europe.

Algorithms and VLSI architectures for low-power mobile face verification

Jean-Luc Nagel, Jean-Luc Nagel, 2005 .

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation

Jean-Luc Nagel, Marc Pons, Stephane Emery, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Maximum delay variation temperature-aware standard cell design

Jean-Luc Nagel, Christian Piguet, Marc Pons, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits

Luca Benini, Enrico Macii, Massimo Poncino, 2010, J. Low Power Electron..

Comparison of feature extraction techniques for face verification using elastic graph matching on low-power mobile devices

Jean-Luc Nagel, Fausto Pellandini, M. Ansorge, 2003, The IEEE Region 8 EUROCON 2003. Computer as a Tool..

Face Authentification for Low-Power Mobile Devices

Jean-Luc Nagel, Patrick Stadelmann, 2007 .

A low-complexity video coder based on the Discrete Walsh Hadamard Transform

Jean-Luc Nagel, Fausto Pellandini, Michael Ansorge, 2000, 2000 10th European Signal Processing Conference.

Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation

Jean-Luc Nagel, Christian Piguet, Marc Pons, 2013, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS).