S. Mettler

Verification of CDM circuit simulation using an ESD evaluation circuit

Wolfgang Fichtner, Wolfgang Wilkening, Ning Qu, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Characterization and modeling of transient device behavior under CDM ESD stress

G. Groeseneken, H. Gieser, M. Etherton, 2004, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Study of CDM specific effects for a smart power input protection structure

Wolfgang Wilkening, Ning Qu, Horst A. Gieser, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Modular approach of a high current MOS compact model for circuit-level ESD simulation including transient gate coupling behavior

Wolfgang Fichtner, S. Mettler, W. Wilkening, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior

W. Fichtner, H. Wolf, S. Mettler, 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

Test circuits for fast and reliable assessment of CDM robustness of I/O stages

Michael Graf, Wolfgang Wilkening, Wolfgang Stadler, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Analysis of lateral DMOS power devices under ESD stress conditions

Wolfgang Fichtner, S. Mettler, W. Wilkening, 2000 .

Characterization and optimization of a bipolar ESD-device by measurements and simulations

W. Fichtner, H. Gieser, H. Wolf, 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions

W. Fichtner, H. Wolf, S. Mettler, 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

Surface mobility in silicon at large operating temperature

W. Fichtner, L. Colalongo, Giorgio Baccarani, 2002, International Conferencre on Simulation of Semiconductor Processes and Devices.

Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection

P. Pfaffli, S. Mettler, M. Schenkel, 2000, 30th European Solid-State Device Research Conference.