Chien-Chou Chen

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

P. Tzeng, Shang-Chun Chen, Y. Hsin, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection

Wei Lin, Po-Chiang Wang, C. Chien, 2019, International Symposium on Microelectronics.

Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration

J. H. Lau, Ming-Jer Kao, Tzu-Kun Ku, 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

Sheng-Tsai Wu, John H. Lau, T.-H. Chen, 2011 .

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

John H. Lau, Ming-Jer Kao, Tzu-Kun Ku, 2011 .

Design, fabrication, and calibration of stress sensors embedded in a TSV interposer in a 300mm wafer

Sheng-Tsai Wu, Heng-Chieh Chien, J. H. Lau, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.