M. Ikeda

I-031 A Study of Parallel Encoding Framework for UHDTV

Takashi Sano, Atsushi Shimizu, Mitsuo Ikeda, 2014 .

HDTV Video Encoder Architecture

Toshio Kondo, Takeshi Ogura, Mitsuo Ikeda, 1998 .

Highly accurate de-jittering scheme for broadcast quality video transmission

Yoshiyuki Yashima, Mitsuo Ikeda, Jiro Naganuma, 2006, Systems and Computers in Japan.

High-Level Synthesis Using Given Datapath Information (Special Section on VLSI Design and CAD Algorithms)

Toshiaki Miyazaki, Mitsuo Ikeda, T. Miyazaki, 1993 .

Method of Video Transcoding from MPEG-2 to HEVC with Picture Structure Information

Takeshi Kumaki, Takeshi Ogura, Mitsuo Ikeda, 2016 .

Residue role assignment based transform partition predetermination on HEVC

Atsushi Shimizu, Jia Su, Mitsuo Ikeda, 2013, 2013 IEEE International Conference on Image Processing.

Concurrent and collaborative methodologies in short TAT LSI design and manufacturing

Toshio Kondo, Hiroshi Kotera, Mitsuo Ikeda, 1999, Systems and Computers in Japan.

A hardware/software concurrent design for a real-time SP@ML MPEG2 video-encoder chip set

Mitsuo Ikeda, Tetsuya Abe, Yutaka Tashiro, 1996, Proceedings ED&TC European Design and Test Conference.

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level

Yoshiyuki Yashima, Ken Nakamura, Mitsuo Ikeda, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI

M. Ikeda, M. Ikeda, 2000 .