I. Kourtev

发表

Clock Skew Scheduling in Rotary Clocking Technology

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

Delay Insertion and Clock Skew Scheduling

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

Clock Skew Scheduling and Clock Tree Synthesis

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

System Timing

Eby G. Friedman, Ivan S. Kourtev, E. Friedman, 2000, The VLSI Handbook.

Clock Skew Scheduling of Level-Sensitive Circuits

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2009 .

4 – Clock Skew Scheduling for Improved Reliability*

Ivan S. Kourtev, I. Kourtev, 2005 .

Clock skew scheduling for improved reliability via quadratic programming

Eby G. Friedman, Ivan S. Kourtev, E. Friedman, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Short Courses in System-on-a-Chip (SoC) design

Donald M. Chiarulli, Steven P. Levitan, Bruce R. Childers, 2003, Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03.

The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment

Eby G. Friedman, Juan J. Becerra, Christopher R. Morton, 1999, 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312).

Noise immunity of digital circuits in mixed-signal smart power systems

Eby G. Friedman, Radu M. Secareanu, Ivan S. Kourtev, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Delay insertion method in clock skew scheduling

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Advanced timing of level-sensitive sequential circuits

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2002, TAU '02.

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

Baris Taskin, Ivan S. Kourtev, B. Taskin, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Timing Optimization Through Clock Skew Scheduling

Baris Taskin, Eby G. Friedman, Ivan S. Kourtev, 2000 .

Topological synthesis of clock trees for VLSI-based DSP systems

Eby G. Friedman, Ivan S. Kourtev, E. Friedman, 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

Simultaneous clock scheduling and buffered clock tree synthesis

Eby G. Friedman, Ivan S. Kourtev, E. Friedman, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking

Baris Taskin, Ivan S. Kourtev, John Wood, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

Synthesis of clock tree topologies to implement nonzero clock skew schedule

E. Friedman, I. Kourtev, 1999 .