Javier de San Pedro

Mining structured petri nets for the visualization of process behavior

Jordi Cortadella, Javier de San Pedro, 2016, SAC.

Physical-aware system-level design for tiled hierarchical chip multiprocessors

Jordi Cortadella, Jordi Petit, Nikita Nikitin, 2013, ISPD '13.

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors

Jordi Cortadella, Nikita Nikitin, Javier de San Pedro, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analytical Performance Modeling of Hierarchical Interconnect Fabrics

Josep Carmona, Jordi Cortadella, Nikita Nikitin, 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

Integrating formal verification in an online judge for e-Learning logic circuit design

Josep Carmona, Jordi Cortadella, Jordi Petit, 2012, SIGCSE '12.

Log-Based Simplification of Process Models

Josep Carmona, Jordi Cortadella, Javier de San Pedro, 2015, BPM.

A hierarchical approach for generating regular floorplans

Jordi Cortadella, Antoni Roca, Javier de San Pedro, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Physical planning for the architectural exploration of large-scale chip multiprocessors

Jordi Cortadella, Jordi Petit, Nikita Nikitin, 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

Specification Mining for Asynchronous Controllers

Jordi Cortadella, Thomas Bourgeat, Javier de San Pedro, 2016, 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

Discovering Duplicate Tasks in Transition Systems for the Simplification of Process Models

Jordi Cortadella, Javier de San Pedro, 2016, BPM.