S. Nandy

发表

VLSI Design and ASPDAC Technical Program Committee

Dinesh Bhatia, Rajiv V. Joshi, Daniel D. Gajski, 2002 .

Architectural Synthesis of Low-Power Computational Engines for LMS Adaptive Filtering

S. K. Nandy, S. Ramanathan, V. Visvanathan, 1998 .

Enhancing speedup in network processing applications by exploiting instruction reuse with flow aggregation

S. Nandy, G. Surendra, Subhasish Banerjee, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

DFG Partitioning Algorithms for Coarse Grained Reconfigurable Array Assisted RTL Simulation Accelerators

S. Nandy, I. Mahapatra, Utkarsh Agarwal, 2018, 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).

Towards Accelerated Genome Informatics on Parallel HPC Platforms: The ReneGENE-GI Perspective

D. Pal, S. Nandy, S. Natarajan, 2019, Journal of Signal Processing Systems.

High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures

S. K. Nandy, H. S. Jamadagni, David Guevorkian, 2009, 2009 International Symposium on Systems, Architectures, Modeling, and Simulation.

Architectural Synthesis of Computational Engines for Subband Adaptive Filtering

S. K. Nandy, S. Ramanathan, V. Visvanathan, 1999, J. VLSI Signal Process..

Applying Modified Householder Transform to Kalman Filter

Rainer Leupers, Ranjani Narayan, Anupam Chattopadhyay, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Compiling HPC Kernels for the REDEFINE CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2016, IEEE Transactions on Parallel and Distributed Systems.

Task Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architectures with an Application on Control of Propulsion System

Ranjani Narayan, Philippe Baufreton, Eric Feron, 2019, 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC).

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat

S. K. Nandy, Ranjani Narayan, Arnab Kumar Biswas, 2015, Circuits Syst. Signal Process..

Energy aware synthesis of application kernels through composition of data-paths on a CGRA

Kavitha T. Madhu, S. K. Nandy, Ranjani Narayan, 2017, Integr..

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Joseph R. Cavallaro, Xinmiao Zhang, G. Falcão, 2022, IEEE Communications Surveys & Tutorials.

Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design pdf

S. K. Nandy, Ranjani Narayan, Anupam Chattopadhyay, 2016, ArXiv.

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations

S. K. Nandy, Ranjani Narayan, Farhad Merchant, 2015, 2015 28th International Conference on VLSI Design.

SIMAAH: RTL simulation accelerator for complex SoC's

S. K. Nandy, Santhi Natarajan, S. Nalesh, 2015, 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).

Experimental Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architecture

S. K. Nandy, Ranjani Narayan, Francois Neumann, 2018, 2018 IEEE/AIAA 37th Digital Avionics Systems Conference (DASC).

Task allocation of safety-critical applications on reconfigurable multi-core architectures

S. K. Nandy, Ranjani Narayan, Francois Neumann, 2017, 2017 IEEE/AIAA 36th Digital Avionics Systems Conference (DASC).

REDEFINE: Runtime reconfigurable polymorphic ASIC

S. K. Nandy, Ranjani Narayan, Alexander Fell, 2009, TECS.

A Cost Effective Pipelined Divider for Double Precision Floating Point Number

S. K. Nandy, Jayanta Biswas, Sandeep B. Singh, 2006, IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06).

REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores

S. K. Nandy, Ranjani Narayan, Gopinath Mahale, 2016, IEEE Transactions on Parallel and Distributed Systems.

Hardware Solution for Real-Time Face Recognition

S. Bhattacharya, S. K. Nandy, Ranjani Narayan, 2015, 2015 28th International Conference on VLSI Design.

Factorization of Boolean Polynomials: Parallel Algorithms and Experimental Evaluation

S. K. Nandy, Denis K. Ponomaryov, Soumyendu Raha, 2021, Programming and Computer Software.

Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network

H.S. Jamadagni, S.K. Nandy, G. Garga, 2008, 2008 International Symposium on System-on-Chip.

An Input Triggered Polymorphic ASIC for H.264 Decoding

S. K. Nandy, Ranjani Narayan, Mythri Alle, 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.

Flexible resource allocation and management for application graphs on ReNÉ MPSoC

Ranjani Narayan, Anuj Rao, Saptarsi Das, 2016, PARMA-DITAM '16.

Towards Accelerated Genome Informatics on Parallel HPC Platforms: The ReneGENE-GI Perspective

S. K. Nandy, Santhi Natarajan, N. Krishna Kumar, 2020, J. Signal Process. Syst..

ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs

S. K. Nandy, Santhi Natarajan, N. Krishna Kumar, 2018, ARC.

Table of Contents 29 th Annual IEEE Conference on Local Computer Networks

Klaus Wehrle, K. Kinoshita, Marcel Waldvogel, 2004 .

On the Correctness of Program Execution When Cache Coherence Is Maintained Locally at Data-Sharing Boundaries in Distributed Shared Memory Multiprocessors

H. Sarojadevi, S. K. Nandy, S. Balakrishnan, 2004, International Journal of Parallel Programming.

Reconfigurable Filter Coprocessor Architecture for DSP Applications

S. K. Nandy, S. Ramanathan, V. Visvanathan, 2000, J. VLSI Signal Process..

Power minimization using control generated clocks

S. K. Nandy, M. Srikanth Rao, S. Nandy, 2000, Proceedings 37th Design Automation Conference.

Controller redesign based clock and register power minimization

M. SrikunthRao, Soumitra K. Nandy, S. Nandy, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Modeling multi-threaded architectures in PAMELA for real-time high performance applications

Arjan J. C. van Gemund, S. K. Nandy, S. Balakrishnan, 1997, Proceedings Fourth International Conference on High-Performance Computing.

Framework for Enabling Highly Available Distributed Applications for Utility Computing

S. K. Nandy, Ranjani Narayan, J. Lakshmi, 2006, ISPA.

Arbitrary precision arithmetic-SIMD style

S. K. Nandy, S. Balakrishnan, S. Nandy, 1998, Proceedings Eleventh International Conference on VLSI Design.

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

Bharadwaj S. Amrutur, S. K. Nandy, Srihari Makineni, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).