Evangeline F. Y. Young

发表

A robust approach for process variation aware mask optimization

Evangeline F. Y. Young, Jian Kuang, Wing-Kai Chow, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Cell density-driven detailed placement with displacement constraint

Evangeline F. Y. Young, Xu He, Jian Kuang, 2014, ISPD '14.

An efficient layout decomposition approach for Triple Patterning Lithography

Evangeline F. Y. Young, Jian Kuang, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Voltage island-driven floorplanning

Evangeline F. Y. Young, Qiang Ma, 2007, ICCAD 2007.

GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets

Evangeline F. Y. Young, Bei Yu, Zihao Deng, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An exact algorithm for the construction of rectilinear steiner minimum trees among complex obstacles

Tao Huang, Evangeline F. Y. Young, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

A fast machine learning-based mask printability predictor for OPC acceleration

Evangeline F. Y. Young, Bentian Jiang, Jinglei Yang, 2019, ASP-DAC.

GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets

Evangeline F. Y. Young, Yuzhe Ma, Haoyu Yang, 2018, Design Automation Conference.

Analog placement with common centroid and 1-D symmetry constraints

Evangeline F. Y. Young, Linfu Xiao, 2009, 2009 Asia and South Pacific Design Automation Conference.

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A two-step search engine for large scale boolean matching under NP3 equivalence

Evangeline F. Y. Young, Gengjie Chen, Chak-Wa Pui, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Multi-bend bus driven floorplanning

Evangeline F. Y. Young, Jill H. Y. Law, 2005, ISPD '05.

Slicing floorplans with boundary constraint

Evangeline F. Y. Young, Martin D. F. Wong, D. F. Wong, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Slicing Floorplan Orientation

Evangeline F. Y. Young, 2016, Encyclopedia of Algorithms.

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

Evangeline F. Y. Young, Qiang Ma, Linfu Xiao, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Handling soft modules in general nonslicing floorplan usingLagrangian relaxation

Evangeline F. Y. Young, W. S. Luk, Chris C. N. Chu, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Practical placement and routing techniques for analog circuit designs

Evangeline F. Y. Young, Kong-Pang Pun, Linfu Xiao, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

An Effective Chemical Mechanical Polishing Fill Insertion Approach

Evangeline F. Y. Young, Jian Kuang, Yande Jiang, 2016, ACM Trans. Design Autom. Electr. Syst..

A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing

Evangeline F. Y. Young, Hui Kong, Martin D. F. Wong, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Interconnect-driven floorplanning by searching alternative packings

Evangeline F. Y. Young, Hai Zhou, Chiu-Wing Sham, 2003, ASP-DAC '03.

An Effective Chemical Mechanical Polishing Filling Approach

Evangeline F. Y. Young, Jian Kuang, Yande Jiang, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Post-Placement Voltage Island Generation

Evangeline F. Y. Young, Mario K. Y. Leung, Eric K. I. Chio, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs

Evangeline F. Y. Young, Gengjie Chen, Jian Kuang, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Slicing floorplans with boundary constraints

Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Multi-bend bus driven floorplanning

Evangeline F. Y. Young, Jill H. Y. Law, 2005, ISPD '05.

Routability-driven and fence-aware legalization for mixed-cell-height circuits

Evangeline F. Y. Young, Gengjie Chen, Wing-Kai Chow, 2018, DAC.

Legalization algorithm for multiple-row height standard cell design

Evangeline F. Y. Young, Wing-Kai Chow, Chak-Wa Pui, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design

Evangeline F. Y. Young, Jian Kuang, Bei Yu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Congestion prediction in early stages

Evangeline F. Y. Young, Chiu-Wing Sham, 2005, SLIP '05.

A dual-MST approach for clock network synthesis

Evangeline F. Y. Young, Wing-Kai Chow, Chiu-Wing Sham, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Clustering based acyclic multi-way partitioning

Evangeline F. Y. Young, Wai-Kei Mak, Eric S. H. Wong, 2003, GLSVLSI '03.

Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning

Evangeline F. Y. Young, Yuzhe Ma, Haoyu Yang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analog placement with symmetry and other placement constraints

Evangeline F. Y. Young, Chris C. N. Chu, Yiu-Cheong Tam, 2006, ICCAD.

An effective triple patterning aware grid-based detailed routing approach

Evangeline F. Y. Young, Zhiqing Liu, Chuangwen Liu, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond

Evangeline F. Y. Young, Jian Kuang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Congestion prediction in floorplanning

Evangeline F. Y. Young, Chiu-Wing Sham, 2005, ASP-DAC.

Planning Massive Interconnects in 3-D Chips

Evangeline F. Y. Young, Jens Lienig, Johann Knechtel, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fence-aware detailed-routability driven placement

Evangeline F. Y. Young, Jian Kuang, Wing-Kai Chow, 2017, 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Slicing Floorplan Orientation.

Evangeline F. Y. Young, 2008 .

Placement and Routing for Cross-Referencing Digital Microfluidic Biochips

Evangeline F. Y. Young, Zigang Xiao, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm

Evangeline F. Y. Young, Gengjie Chen, Peishan Tu, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Handling routability in floorplan design with twin binary trees

Evangeline F. Y. Young, Chris C. N. Chu, Steve T. W. Lai, 2009, Integr..

Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree

Evangeline F. Y. Young, Liang Li, Zaichen Qian, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters

Evangeline F. Y. Young, Jian Kuang, 2014, ISPD '14.

Ripple: A Robust and Effective Routability-Driven Placer

Tao Huang, Evangeline F. Y. Young, Xu He, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Routability driven floorplanner with buffer block planning

Evangeline F. Y. Young, Chiu-Wing Sham, 2002, ISPD '02.

Twin binary sequences: a non-redundant representation for general non-slicing floorplan

Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen, 2002, ISPD '02.

FIT: Fill Insertion Considering Timing

Evangeline F. Y. Young, Ran Chen, Xiaopeng Zhang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Ripple: An effective routability-driven placer by iterative cell movement

Tao Huang, Evangeline F. Y. Young, Xu He, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)

Evangeline F. Y. Young, Gengjie Chen, Yuzhe Ma, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Triple patterning lithography aware optimization for standard cell based design

Evangeline F. Y. Young, Jian Kuang, Wing-Kai Chow, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Non-rectangular shaping and sizing of soft modules in floorplan design

Evangeline F. Y. Young, Chris C. N. Chu, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Nonrectangular shaping and sizing of soft modules for floorplan-design improvement

Evangeline F. Y. Young, Chris C. N. Chu, C. Chu, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

General purpose cross-referencing Microfluidic Biochip with reduced pin-count

Evangeline F. Y. Young, Jackson H. C. Yeung, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

On extending slicing floorplan to handle L/T-shaped modules andabutment constraints

Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Grid-to-ports clock routing for high performance microprocessor designs

Evangeline F. Y. Young, Cliff C. N. Sze, Haitong Tian, 2011, ISPD '11.

Fixed-outline thermal-aware 3D floorplanning

Evangeline F. Y. Young, Jingyu Xu, Subarna Sinha, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization

Evangeline F. Y. Young, Bei Yu, Hang Zhang, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Multi-voltage floorplan design with optimal voltage assignment

Evangeline F. Y. Young, Zaichen Qian, 2009, ISPD '09.

TCG-based multi-bend bus driven floorplanning

Evangeline F. Y. Young, Tilen Ma, Tilen Ma, 2008, 2008 Asia and South Pacific Design Automation Conference.

Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs

Evangeline F. Y. Young, Jian Kuang, Wing-Kai Chow, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Floorplan area minimization using Lagrangian relaxation

Evangeline F. Y. Young, W. S. Luk, Chris C. N. Chu, 2000, ISPD '00.

3-D floorplanning using labeled tree and dual sequences

Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, 2008, ISPD '08.

Temporal logic replication for dynamically reconfigurable FPGA partitioning

Evangeline F. Y. Young, Wai-Kei Mak, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Attacking Split Manufacturing from a Deep Learning Perspective

Evangeline F. Y. Young, Ozgur Sinanoglu, Haoyu Yang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

A monte-carlo floating-point unit for self-validating arithmetic

Evangeline F. Y. Young, Philip Heng Wai Leong, Jackson H. C. Yeung, 2011, FPGA '11.

Row-structure stencil planning approaches for E-beam lithography with overlapped characters

Evangeline F. Y. Young, Jian Kuang, 2016, Integr..

How good are slicing floorplans?

Evangeline F. Y. Young, Martin D. F. Wong, 1997, Integr..

Global Interconnect Planning

Evangeline F. Y. Young, Cheng-Kok Koh, Yao-Wen Chang, 2008, Handbook of Algorithms for Physical Design Automation.

How good are slicing floorplans?

Evangeline F. Y. Young, Martin D. F. Wong, D. F. Wong, 1997, ISPD '97.

Wire Retiming Problem With Net Topology Optimization

Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Proceedings of the 2015 Symposium on International Symposium on Physical Design

Evangeline F. Y. Young, Azadeh Davoodi, 2015, ISDP.

Simultaneous template optimization and mask assignment for DSA with multiple patterning

Evangeline F. Y. Young, Junjie Ye, Jian Kuang, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

SRP: simultaneous routing and placement for congestion refinement

Evangeline F. Y. Young, Xu He, Wing-Kai Chow, 2013, ISPD '13.

Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search

Evangeline F. Y. Young, Gengjie Chen, Chak-Wa Pui, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Voltage island-driven floorplanning

Evangeline F. Y. Young, Qiang Ma, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Routability-driven floorplanner with buffer block planning

Evangeline F. Y. Young, Chiu-Wing Sham, Chiu-Wing Sham, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

CrossRouter: A droplet router for cross-referencing digital microfluidic biochips

Evangeline F. Y. Young, Zigang Xiao, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems

Evangeline F. Y. Young, Gang Wu, Chak-Wa Pui, 2019, 2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

A new and efficient congestion evaluation model in floorplanning: wire density control with twin binary trees

Evangeline F. Y. Young, Chris C. N. Chu, Steve T. W. Lai, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Analog placement with common centroid constraints

Evangeline F. Y. Young, Kong-Pang Pun, Qiang Ma, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Layout hotspot detection with feature tensor generation and deep biased learning

Evangeline F. Y. Young, Haoyu Yang, Yi Zou, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Slicing floorplan with clustering constraints

Evangeline F. Y. Young, Wing Seung Yuen, W. S. Yuen, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

Test scheduling for built-in self-tested embedded SRAMs with data retention faults

Evangeline F. Y. Young, Qiang Xu, André Ivanov, 2007, IET Comput. Digit. Tech..

3D floorplan representations: Corner links and partial order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Performance-driven register insertion in placement

Evangeline F. Y. Young, Dennis K. Y. Tong, 2004, ISPD '04.

CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model

Evangeline F. Y. Young, Jinwei Liu, Fangzhou Wang, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Construction of rectilinear Steiner minimum trees with slew constraints over obstacles

Tao Huang, Evangeline F. Y. Young, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Crosslink insertion for variation-driven clock network construction

Evangeline F. Y. Young, Haitong Tian, Fuqiang Qian, 2012, GLSVLSI '12.

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2018, ACM Trans. Design Autom. Electr. Syst..

On the construction of universal series-parallel functions for logic module design

Evangeline F. Y. Young, Martin D. F. Wong, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

A unified method to handle different kinds of placement constraints in floorplan design

Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Lithography hotspot detection: From shallow to deep learning

Evangeline F. Y. Young, Bei Yu, Haoyu Yang, 2017, 2017 30th IEEE International System-on-Chip Conference (SOCC).

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection pdf

Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg, 2019, ArXiv.

Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration

Evangeline F. Y. Young, Chak-Wa Pui, Peishan Tu, 2018, ACM Great Lakes Symposium on VLSI.

Area reduction by deadspace utilization on interconnect optimized floorplan

Evangeline F. Y. Young, Chiu-Wing Sham, Chiu-Wing Sham, 2007, TODE.

An optimal algorithm for layer assignment of bus escape routing on PCBs

Evangeline F. Y. Young, Martin D. F. Wong, Qiang Ma, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Generation of universal series-parallel Boolean functions

Evangeline F. Y. Young, Martin D. F. Wong, Chris C. N. Chu, 1999, JACM.

Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach

Tao Huang, Evangeline F. Y. Young, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Optimal cell flipping in placement and floorplanning

Evangeline F. Y. Young, Chris C. N. Chu, Chiu-Wing Sham, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2010, ISPD '10.

Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems

Evangeline F. Y. Young, Chak-Wa Pui, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Temporal logic replication for dynamically reconfigurable FPGA partitioning

Evangeline F. Y. Young, Wai-Kei Mak, Wai-Kei Mak, 2002, ISPD '02.

Block flipping and white space distribution for wirelength minimization

Evangeline F. Y. Young, Chiu-Wing Sham, Chiu-Wing Sham, 2009, Integr..

Optimization for Multiple Patterning Lithography with cutting process and beyond

Evangeline F. Y. Young, Jian Kuang, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Network flow-based power optimization under timing constraints in MSV-driven floorplanning

Evangeline F. Y. Young, Qiang Ma, 2008, ICCAD 2008.

Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Tao Huang, Evangeline F. Y. Young, Yan Jiang, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees

Tao Huang, Evangeline F. Y. Young, Liang Li, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Structural planning of 3D-IC interconnects by block alignment

Evangeline F. Y. Young, Jens Lienig, Johann Knechtel, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Block alignment in 3D floorplan using layered TCG

Evangeline F. Y. Young, Jill H. Y. Law, Royce L. S. Ching, 2006, GLSVLSI '06.

Slicing floorplan with clustering constraint

Evangeline F. Y. Young, Wing Seung Yuen, W. S. Yuen, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Post-placement voltage island generation

Evangeline F. Y. Young, Chris C. N. Chu, Royce L. S. Ching, 2006, ICCAD.

A Fast Hypergraph Bipartitioning Algorithm

Evangeline F. Y. Young, Wenzan Cai, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Congestion estimation with buffer planning in floorplan design

Evangeline F. Y. Young, Chiu-Wing Sham, Wai-Chiu Wong, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Bilinear Lithography Hotspot Detection

Evangeline F. Y. Young, Fengyuan Zhu, Bei Yu, 2017, ISPD.

Shuttle mask floorplanning with modified alpha-restricted grid

Evangeline F. Y. Young, Royce L. S. Ching, 2006, GLSVLSI '06.

Session details: Synthesis for FPGAs

Evangeline F. Y. Young, Kia Bazargan, K. Bazargan, 2005, ASP-DAC '05.

Obstacle-avoiding rectilinear Steiner tree construction

Evangeline F. Y. Young, Liang Li, Liang Li, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness

Evangeline F. Y. Young, Chung-Kuan Cheng, Renshen Wang, 2010, TODE.

Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration

Evangeline F. Y. Young, Chak-Wa Pui, Peishan Tu, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Postgrid Clock Routing for High Performance Microprocessor Designs

Evangeline F. Y. Young, Cliff C. N. Sze, Haitong Tian, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)

Evangeline F. Y. Young, Ka-Chun Lam, Wai-Chung Tang, 2014, FPGA.

MSV-Driven Floorplanning

Evangeline F. Y. Young, Hai Zhou, Qiang Ma, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Placement constraints in floorplan design

Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Incorporating cut redistribution with mask assignment to enable 1D gridded design

Evangeline F. Y. Young, Jian Kuang, Bei Yu, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems

Evangeline F. Y. Young, Chak-Wa Pui, 2020, ACM Trans. Design Autom. Electr. Syst..

Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning

Evangeline F. Y. Young, Yuan Zhou, Zhiru Zhang, 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Retiming with Interconnect and Gate Delay

Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu, 2003, ICCAD.

Slicing Floorplan Orientation

Evangeline F. Y. Young, 2008, Encyclopedia of Algorithms.

Postplacement Voltage Island Generation

Evangeline F. Y. Young, Mario K. Y. Leung, Eric K. I. Chio, 2012 .

Floorplan Representations

Evangeline F. Y. Young, 2008, Handbook of Algorithms for Physical Design Automation.

Minimizing thermal gradient and pumping power in 3D IC liquid cooling network design

Evangeline F. Y. Young, Gengjie Chen, Jian Kuang, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction

Evangeline F. Y. Young, Gengjie Chen, Bentian Jiang, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Analog placement with common centroid constraints

Evangeline F. Y. Young, Qiang Ma, K. P. Pun, 2007, ICCAD 2007.

Area reduction by deadspace utilization on interconnect optimized floorplan

Evangeline F. Y. Young, Chiu-Wing Sham, 2007, TODE.

Congestion prediction in early stages of physical design

Evangeline F. Y. Young, Chiu-Wing Sham, Jingwei Lu, 2009, TODE.

Dim Sum: Light Clock Tree by Small Diameter Sum

Evangeline F. Y. Young, Gengjie Chen, Gengjie Chen, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Overlapping-aware throughput-driven stencil planning for E-beam lithography

Evangeline F. Y. Young, Jian Kuang, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Reducing pin count on cross-referencing Digital Microfluidic Biochip

Evangeline F. Y. Young, C. S. Choy, Ho Chuen Jackson Yeung, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Retention-Aware Test Scheduling for BISTed Embedded SRAMs

Evangeline F. Y. Young, Qiang Xu, Baosheng Wang, 2006, Eleventh IEEE European Test Symposium (ETS'06).

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs

Evangeline F. Y. Young, Gengjie Chen, Jian Kuang, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

VLSI layout hotspot detection based on discriminative feature extraction

Evangeline F. Y. Young, Haoyu Yang, Bei Yu, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Detailed routing by sparse grid graph and minimum-area-captured path search

Evangeline F. Y. Young, Gengjie Chen, Bentian Jiang, 2019, ASP-DAC.

Ripple 2.0: High quality routability-driven placement via global router integration

Tao Huang, Evangeline F. Y. Young, Xu He, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Slicing floorplans with range constraint

Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang, 1999, ISPD '99.

Optimizing wirelength and routability by searching alternative packings in floorplanning

Evangeline F. Y. Young, Hai Zhou, Chiu-Wing Sham, 2008, TODE.

Droplet-routing-aware module placement for cross-referencing biochips

Evangeline F. Y. Young, Zigang Xiao, 2010, ISPD '10.

Twin binary sequences: a non-redundant representation for general non-slicing floorplan

Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen, 2002, ISPD '02.

Multivoltage Floorplan Design

Evangeline F. Y. Young, Qiang Ma, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Slicing floorplans with pre-placed modules

Evangeline F. Y. Young, Martin D. F. Wong, 1998, ICCAD.

Fast buffer planning and congestion optimization in interconnect-driven floorplanning

Evangeline F. Y. Young, Keith W. C. Wong, 2003, ASP-DAC '03.

Fast detection of largest repeating layout pattern

Evangeline F. Y. Young, James P. Shiely, Jingsong Chen, 2019, Advanced Lithography.

Network flow-based power optimization under timing constraints in MSV-driven floorplanning

Evangeline F. Y. Young, Qiang Ma, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Fixed-parameter tractable algorithms for optimal layout decomposition and beyond

Evangeline F. Y. Young, Jian Kuang, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses

Evangeline F. Y. Young, Dan Zheng, Gengjie Chen, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning

Evangeline F. Y. Young, Junjie Ye, Jian Kuang, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Placement: From Wirelength to Detailed Routability

Evangeline F. Y. Young, Wing-Kai Chow, 2016, IPSJ Trans. Syst. LSI Des. Methodol..

Integrated floorplanning and interconnect planning

Evangeline F. Y. Young, Hai Zhou, Hung-Ming Chen, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm

Evangeline F. Y. Young, Gengjie Chen, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Proceedings of the 2016 on International Symposium on Physical Design

Evangeline F. Y. Young, Mustafa Ozdal, 2016, ISPD.

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement

Evangeline F. Y. Young, Yang Guo, Yao Wang, 2016, TODE.

Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology

Evangeline F. Y. Young, Azadeh Davoodi, 2016, ACM Trans. Design Autom. Electr. Syst..

Slicing floorplans with range constraint

Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Timing driven routing tree construction

Evangeline F. Y. Young, Wing-Kai Chow, Peishan Tu, 2017, 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

Building up End-to-end Mask Optimization Framework with Self-training

Evangeline F. Y. Young, Bentian Jiang, Lixin Liu, 2021, ISPD.

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation

Evangeline F. Y. Young, Ozgur Sinanoglu, Johann Knechtel, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment

Evangeline F. Y. Young, Chak-Wa Pui, Xiaopeng Zhang, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning

Evangeline F. Y. Young, Gengjie Chen, Jinwei Liu, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation

Evangeline F. Y. Young, Haoyu Yang, Xiaopeng Zhang, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Analog Placement with Symmetry and Other Placement Constraints

Evangeline F. Y. Young, Yiu-Cheong Tam, C. Chu, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Adversarial Perturbation Attacks on ML-based CAD

Evangeline F. Y. Young, R. Karri, Haoyu Yang, 2020 .

Crosslink insertion for variation-driven clock network construction

Evangeline F. Y. Young, Fuqiang Qian, Haitong Tian, 2012, GLSVLSI '12.

Obstacle-avoiding rectilinear Steiner tree construction

Evangeline F. Y. Young, Liang Li, 2008, ICCAD 2008.

Retiming with Interconnect and Gate Delay

Evangeline F. Y. Young, Chris Chu, Sampath Dechu, 2003, ICCAD 2003.

Xplace: an extremely fast and extensible global placement framework

Evangeline F. Y. Young, Martin D. F. Wong, Lixin Liu, 2022, DAC.

Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization

Evangeline F. Y. Young, Hang Zhang, Yuzhe Ma, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

PROS

Evangeline F. Y. Young, D. J. Huang, Jingsong Chen, 2020, Proceedings of the 39th International Conference on Computer-Aided Design.

PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning

Evangeline F. Y. Young, Jingsong Chen, Evangeline F.Y. Young, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Fast buffer planning and congestion optimization in interconnect-driven floorplanning

Evangeline F. Y. Young, E.F.Y. Young, K.W.C. Wong, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

Challenges and Approaches in VLSI Routing

Evangeline F. Y. Young, D. Pan, Yih-Lang Li, 2022, ISPD.

FastPass: Fast Pin Access Analysis with Incremental SAT Solving

Evangeline F. Y. Young, Fangzhou Wang, Jinwei Liu, 2023, ISPD.

PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning

Evangeline F. Y. Young, D. J. Huang, Jingsong Chen, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A2-ILT: GPU accelerated ILT with spatial attention mechanism

Evangeline F. Y. Young, Martin D. F. Wong, Bentian Jiang, 2022, DAC.

Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network

Evangeline F. Y. Young, Yuzhe Ma, Bei Yu, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Layout Pattern Generation and Legalization with Generative Learning Models

Evangeline F. Y. Young, Xiaopeng Zhang, Evangeline F.Y. Young, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Area reduction on interconnect optimized floorplan using deadspace utilization

Evangeline F. Y. Young, Chiu-Wing Sham, E.F.Y. Young, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning

Evangeline F. Y. Young, Martin D. F. Wong, Xinshi Zang, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement

Evangeline F. Y. Young, Jianye Hao, Zhitang Chen, 2022, 2022 IEEE International Test Conference (ITC).

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method

Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Adversarial Perturbation Attacks on ML-based CAD

Evangeline F. Y. Young, R. Karri, Haoyu Yang, 2020, ACM Trans. Design Autom. Electr. Syst..

Slicing floorplans with pre-placed modules

Evangeline F. Y. Young, D. F. Wong, D.F. Wong, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).