S. Verhaegen

Simulation of patterning-induced circuit performance variability

G. Vandenberghe, J. Ramos, A. Nackaerts, 2006, 2006 IEEE International Conference on IC Design and Technology.

Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics

M. Van Hove, T. Chiarella, I. Debusschere, 2006, 2006 IEEE International Conference on Microelectronic Test Structures.

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

G. Vandenberghe, J. Finders, S. Verhaegen, 2010, Advanced Lithography.

Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell

Naoto Horiguchi, Anabela Veloso, S. Locorotondo, 2010 .

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

R. Rooyackers, M. Van Hove, K. Ronse, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).