S. Biesemans

发表

Simulation of patterning-induced circuit performance variability

G. Vandenberghe, J. Ramos, A. Nackaerts, 2006, 2006 IEEE International Conference on IC Design and Technology.

A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications

R. Mahnkopf, S. Biesemans, L. K. Han, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics

M. Van Hove, T. Chiarella, I. Debusschere, 2006, 2006 IEEE International Conference on Microelectronic Test Structures.

Variability and technology aware SRAM Product yield maximization

A. Mercha, P. Roussel, D. Verkest, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Hot-carrier degradation on the analogue/RF performances of a 90nm RF-CMOS technology demonstrated in a 900MHz low-power LNA

P. Wambacq, A. Mercha, S. Decoutere, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

On the effective mobility for electrons in MOS inversion channels

S. Biesemans, K. De Meyer, K. De Meyer, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

Four-Terminal FinFET Device Technology

K. Endo, T. Matsukawa, S. O'uchi, 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

Scalability and biasing strategy for CMOS with active well bias

Bomy Chen, R. Dennard, Chih-Yung Lin, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

A high performance CMOS device with inverter delay 13 ps at 1.2 V power supply

C. Wann, S. Biesemans, Yao-Ching Cheng, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

CMOS with active well bias for low-power and RF/analog applications

R. Mahnkopf, R. Dennard, S. Biesemans, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

R. Rooyackers, Liesbeth Witters, C. Ortolland, 2009, 2009 Proceedings of ESSCIRC.

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

G. Knoblinger, J. Gill, S. Biesemans, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Spice simulation of 0.18 /spl mu/m CMOS ring oscillators using physical models for capacitance and series resistance

S. Biesemans, K. De Meyer, S. Kubicek, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Perspective on Emerging Devices and their Impact on Scaling Technologies

S. Biesemans, 2005 .

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

B. Parvais, R. Rooyackers, A. Mercha, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-Roughness

R. Rooyackers, A. Mercha, E. Augendre, 2006, 2006 International Electron Devices Meeting.

Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

H. Tigelaar, T. Chiarella, J. Ramos, 2006, 2006 International Electron Devices Meeting.

Multi-gate devices for the 32nm technology node and beyond

R. Rooyackers, A. Mercha, L. Witters, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Review of FINFET technology

N. Collaert, A. Veloso, S. Biesemans, 2009, 2009 IEEE International SOI Conference.

New architectures for deep submicron MOSFETs

S. Biesemans, K. De Meyer, S. Kubicek, 1998, 28th European Solid-State Device Research Conference.

Exploration of the Circuit Potential of Multiple-Gate Field-Effect Transistors

S. Severi, E. Augendre, N. Collaert, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Addressing Key Concerns for Implementation of Ni FUSI into Manufacturing for 45/32 nm CMOS

L. Pantisano, B. Kaczer, H. Tigelaar, 2007, 2007 IEEE Symposium on VLSI Technology.

Assessment of a MOSFET circuit model as a tool for device design down to 0.05 /spl mu/m

S. Biesemans, K. De Meyer, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production

T. Hoffmann, H. Tigelaar, L. Witters, 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

C. Ortolland, L. Witters, H. Bender, 2010, 2010 Symposium on VLSI Technology.

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

R. Rooyackers, T. Skotnicki, N. Collaert, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

0.5 nm EOT low leakage ALD SrTiO3 on TiN MIM capacitors for DRAM applications

S. Van Elshocht, B. Kaczer, H. Bender, 2008, 2008 IEEE International Electron Devices Meeting.

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

R. Rooyackers, N. Collaert, R. Jonckheere, 2004, IEEE Electron Device Letters.

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

R. Rooyackers, M. Van Hove, K. Ronse, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

C. Vrancken, A. Veloso, S. Biesemans, 2006, IEEE Electron Device Letters.

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

R. Rooyackers, G. Eneman, S. Biesemans, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

C. Ortolland, T. Chiarella, W. Vandervorst, 2008, 2008 Symposium on VLSI Technology.

A low-cost 90nm RF-CMOS platform for record RF circuit performance

P. Soussan, P. Wambacq, A. Mercha, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

A systematic study of trade-offs in engineering a locally strained pMOSFET

R. Rooyackers, I. De Wolf, F. Nouri, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

R. Rooyackers, N. Collaert, G. Eneman, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Metal Gate Technology using a Dy2O3 Dielectric Cap Approach for multiple-VT in NMOS FinFETs

S. Van Elshocht, B. Kaczer, P. Lehnen, 2007, 2007 IEEE International SOI Conference.

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

R. Rooyackers, N. Collaert, S. Biesemans, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 Symposium on VLSI Technology.

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

A. Akheyar, T. Chiarella, C. Vrancken, 2008, 2008 Symposium on VLSI Technology.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

R. Rooyackers, E. Augendre, N. Collaert, 2006, 2006 International Electron Devices Meeting.

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

L. Witters, H. Bender, T. Chiarella, 2010, 2010 Symposium on VLSI Technology.

Transport-based dopant metrology in advanced FinFETs

N. Collaert, S. Biesemans, G. Klimeck, 2008, 2008 IEEE International Electron Devices Meeting.

Processing impact on the reliability of single metal dual dielectric (SMDD) gate stacks

R. Degraeve, G. Groeseneken, S. Biesemans, 2009, 2009 IEEE International Reliability Physics Symposium.

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

T. Chiarella, C. Vrancken, A. Veloso, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

R. Rooyackers, B. Kaczer, S. Locorotondo, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

1mA/um-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D

P. Eyben, G. Hellings, L. Witters, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Layout density analysis of FinFETs

N. Collaert, S. Biesemans, K.G. Anil, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Schottky-Barrier Height Lowering by an Increase of the Substrate Doping in PtSi Schottky Barrier Source/Drain FETs

E. Augendre, S. Biesemans, M. Jurczak, 2007, IEEE Electron Device Letters.

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

R. Rooyackers, N. Collaert, S. Biesemans, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

The dependence of channel length on channel width in narrow-channel CMOS devices for 0.35-0.13 μm technologies

J. Slinkman, S. Biesemans, T.B. Hook, 2000, IEEE Electron Device Letters.

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

S. Locorotondo, H. Bender, T. Chiarella, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

B. Parvais, S. Biesemans, T. Schram, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Demonstration of Asymmetric Gate Oxide Thickness 4-Terminal FinFETs

M. Masahara, L. Witters, C. Vrancken, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

S. De Gendt, S. Van Elshocht, A. Akheyar, 2007, 2007 IEEE International Electron Devices Meeting.

Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL

B. Ghyselen, R. Rooyackers, N. Collaert, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

P. Soussan, E. Beyne, C. Huyghebaert, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL

B. Ghyselen, R. Rooyackers, E. Augendre, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Electron Device Letters.

Strain Enhanced nMOS Using In Situ Doped Embedded $\hbox{Si}_{1 - x}\hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

H. Bender, S. Biesemans, D. Shamiryan, 2008, IEEE Electron Device Letters.

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

S. Van Elshocht, P. Lehnen, C. Vrancken, 2007, 2007 IEEE Symposium on VLSI Technology.

Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology

C. Ortolland, A. Akheyar, T. Chiarella, 2006, 2009 Symposium on VLSI Technology.

Ion-implantation-based low-cost Hk/MG process for CMOS low-power application

R. Degraeve, C. Ortolland, W. Vandervorst, 2010, 2010 Symposium on VLSI Technology.

Experimental Investigation of Optimum Gate Workfunction for CMOS Four-Terminal Multigate MOSFETs (MUGFETs)

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Transactions on Electron Devices.

Electric Field Reduced Charging Energies and Two-Electron Bound Excited States of Single Donors in Silicon

N. Collaert, S. Biesemans, G. Klimeck, 2011, 1107.2701.

Tall triple-gate device with TiN/HfO2 gate stack

Paul Zimmerman, Tom Schram, Stefan De Gendt, 2005 .

The Impact of Stacked Cap Layers on Effective Work Function With HfSiON and SiON Gate Dielectrics

S. Van Elshocht, A. Akheyar, S. Biesemans, 2008, IEEE Electron Device Letters.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

E. Augendre, A. Veloso, S. Biesemans, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Optimization of Sub-Melt Laser Anneal: Performance and Reliability

S. Mahapatra, S. Severi, L. Pantisano, 2006, 2006 International Electron Devices Meeting.

Positive and negative bias temperature instability in La2O3 and Al2O3 capped high-k MOSFETs

R. Degraeve, B. Kaczer, A. Akheyar, 2009, 2009 IEEE International Reliability Physics Symposium.

Tall triple-gate devices with TiN/HfO/sub 2/ gate stack

S. De Gendt, N. Collaert, W. Boullart, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

S. Locorotondo, T. Chiarella, C. Vrancken, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..