Pavlos M. Mattheakis

发表

Hardware primitives for the synthesis of multithreaded elastic systems

Giorgos Dimitrakopoulos, Ioannis Seitanidis, Anastasios Psarras, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Timing-Driven and Placement-Aware Multibit Register Composition

Giorgos Dimitrakopoulos, Ioannis Seitanidis, Pavlos M. Mattheakis, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition

Pavlos M. Mattheakis, Christos P. Sotiriou, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Accelerating Intercommunication in Highly Parallel Systems

Ioannis Papaefstathiou, Nikolaos Tampouratzis, Pavlos M. Mattheakis, 2016, ACM Trans. Archit. Code Optim..

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Evolving challenges and techniques for nanometer SoC clock network synthesis

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A polynomial time flow for implementing free-choice Petri-nets

Peter A. Beerel, Pavlos M. Mattheakis, Christos P. Sotiriou, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Logic synthesis of concurrent control specifications

Pavlos M. Mattheakis, Παύλος Ματθαιάκης, 2013 .

Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems

Ioannis Papaefstathiou, Pavlos M. Mattheakis, I. Papaefstathiou, 2013, TACO.

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed

Pavlos M. Mattheakis, Christos P. Sotiriou, Evangelia Kassapaki, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Timing driven incremental multi-bit register composition using a placement-aware ILP formulation

David G. Chinnery, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization

David Z. Pan, Pavlos M. Mattheakis, Subhendu Roy, 2015, ACM Great Lakes Symposium on VLSI.